Diese Arbeit untersucht Aufbau- und Verbindungstechniken auf Basis von Leiterplattentechnologien für Wide-Bandgap-Leistungstransistoren mit schnellen Schaltvorgängen. Mit dem Ziel ein überschwingungsfreies Schalten zu erreichen, werden niederinduktive Konzepte für Zweilevel- und Dreilevel-Inverter im Hinblick auf verschiedene Schichtdicken bzw. Leiterplattentechnologien vorgestellt und diskutiert. Dabei konnte gezeigt werden, dass Schaltzellen unter Berücksichtigung von parasitären Kapazitäten so niederinduktiv gestaltet werden können, dass ein Überschwingen beim Schaltvorgang keine Limitierung mehr darstellt. Neuartige Aufbau- und Verbindungstechniken, wie die Integration der Halbleiter in den Kern der Leiterplatte, können zudem die elektrischen, thermischen und mechanischen Eigenschaften im Vergleich zu konventionellen Bauelementen verbessern. Dünnfilmtechnologien zeigen eine bessere Störfestigkeit bzw. ein geringeres Übersprechen auf andere Signalleitungen. Außerdem wurden Filtermaßnahmen zur Reduzierung von hochfrequenten Störspannungen, die durch kurze Schaltzeiten entstehen, untersucht.
Design of a Low Multi-Loop Inductance Three Level Neutral Point Clamped Converter with GaN HEMTs
(2020)
This work shows a numerical and experimental analysis of a Neutral-Point-Clamp (NPC) three level inverter featuring an ultra low inductance printed circuit board (PCB) design in consideration of the mutual inductive and capacitive couplings. The commutation loops in this design are found to be strongly dependent on the vertical thickness of the used prepregs and the core. For vertical thicknesses ≤ 100 μm capacitive coupling must be taken into account in the switching cell design. Experimental measurements of a test set-up with a total PCB thickness of 400 μm results in commutation loop inductances from 1.4 nH up to 3.1 nH. In this set-up, switching tests without external gate resistor showed only a maximum voltage overshoot of 7% at 800 V. Based on a numerical analysis of the NPC cell we propose a further switching performance improvement with significant smaller parasitic inductance due to the application of novel printed circuit technologies such as the integration of bare dies into the printed circuit board or polyimide as an interlayer dielectric material.
We present a numerical and experimental design study for reducing conducted common mode noise for frequencies below 10MHz generated in switching cells comprising sub-nH commutation loops. Compared to conventional methods of adding external gate resistors our approach does not degrade efficiency. A parallel plate loop design (characterized by a minimum loop inductance and small board area usage) is found suboptimal in terms of conducted EMI compared to a micro-strip line loop geometry. The net ground impedance rather than the net ground inductance is found to mainly contribute to the observed EMI noise.
Wide-bandgap semiconductors such as Silicon Carbide (SiC) or Gallium Nitride (GaN) enable fast switching and high switching frequencies of power electronics. However, this potential can not be exploited due to limitations caused by parasitic elements of packaging and interconnections. This paper shows a possibility to minimize parasitic elements of a half-bridge switching cell with 650 V GaN dies integrated into a printed circuit substrate. A sub-nH commutation loop of 0.5 nH inductance gives superior switching characteristics compared to circuits with packaged dies. Simulation and experimental results of an inverse double pulse test confirm our expectations. This study further reveals additional benefits of the proposed technology in terms of mechanical stability and thermal interfacing to heat sinks compared to circuits with packaged dies.
Power cycling and temperature endurance test of a GaN switching cell with substrate integrated chips
(2019)
We present a reliability study of a half-bridge switching cell with substrate integrated 650 V GaN HEMTs. Power Cycling Testing with a ΔTj of 100 K has revealed thermo-mechanically induced failures of contact vias after more than 220 kcycles. The via failure mode of contact opening is confirmed by reverse-bias pulsed IV-measurements to be primarily triggered by a ΔTj imposed thermal gradient and not by a high Tj. The chip electrical characteristics, however, remained unaffected during Power Cycling. Furthermore, a High Temperature Storage test at 125 °C for 5000 h has shown no changes in the electrical performance of substrate integrated GaN HEMTs.
This paper proposes an ultra-low inductance half-bridge switching cell with substrate integrated 650V GaN bare dies. A vertical parallel-plate waveguide structure with 100 μm layer thickness results in a commutation loop inductance of 0.5 nH resulting in a negligible drain-source voltage overshoot in the inductive load standard pulse test. On the other hand reliable circuit operation requires an assessment of the isolation strength of the thin dielectric layer in the main commutation loop, because critical high local electric fields might occur between the pads. Measurements of the dielectric breakdown voltage followed by a statistical failure analysis provide a characteristic life of 14.7 kV and a 10% quantile of 13.5kV in the Weibull fitted data. This characteristic life depends strongly on the ambient temperature and drops to 4.1kV at 125°C. Additionally, ageing tests show an increasing in dielectric breakdown voltage after 500h, 1000h and 2000h at 125°C high-temperature storage due to resin densification processes.