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We present a numerical and experimental design study for reducing conducted common mode noise for frequencies below 10MHz generated in switching cells comprising sub-nH commutation loops. Compared to conventional methods of adding external gate resistors our approach does not degrade efficiency. A parallel plate loop design (characterized by a minimum loop inductance and small board area usage) is found suboptimal in terms of conducted EMI compared to a micro-strip line loop geometry. The net ground impedance rather than the net ground inductance is found to mainly contribute to the observed EMI noise.
Increasing the switching frequency has been one of the most beneficial advancements in modern power electronics. This trend has been enabled by progress in power semiconductors resulting in increased power densities, efficiencies and control dynamics. The aim of this study is to analyze the influence of three different circuit carrier technologies on switching power loss of 650 V hardswitching GaN devices. Limitations and solutions for half-bridge circuits operating at MHz-switching are investigated by modeling and experiments on a prototype.