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A DDR3 SDRAM test setup implemented on the Griffin III test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests for different manufacturing technologies. The row hammer effect is depending on the number of stress activation cycles. The analysis is extended to an avoidance scheme with refreshes similar to the Target Row Refresh scheme for the DDR4 SDRAM technology.
A DDR2 SDRAM test setup implemented on the Griffin III ATE test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests.
The analysis confirms that the row hammer effect is caused by a charge excitation process depending on the number of stress activation cycles. The stress has to occur in the local neighborhood of the cells under test.
Shallow impurity levels support the responsible charge carrier transport process in the used DDR2 SDRAM technology