TY - CHAP A1 - Höfig, Kai A1 - Zeller, Marc A1 - Schorp, Konstantin T1 - Automated failure propagation using inner port dependency traces T2 - 2015 11th International ACM SIGSOFT Conference on Quality of Software Architectures (QoSA), Mai 2015, Montreal, QC, Canada. N2 - Safety assurance is a major challenge in the design of complex embedded and Cyber-physical Systems. Especially, changes and adoptions during the design or run-time of an embedded system invalidate former safety analyses and require an adaptation of the system's safety analysis models. In this paper, we present a methodology to fill up empty safety analysis artifacts in component fault trees using so-called inner port dependency traces to describe failure propagation. Thus, enabling a imprecise but rapid safety analysis of an entire system at early development stages or during system run-time for the automated certification of Cyber-physical Systems. We evaluate our approach using case study from the automotive domain. KW - Failure propagation KW - Port dependency traces KW - Cyber-physical Systems KW - Software safety Y1 - 2015 SP - 123 EP - 128 ER - TY - CHAP A1 - Höfig, Kai A1 - Armbruster, Michael A1 - Schmidt, Reiner T1 - A vehicle control platform as safety element out of context. T2 - HiPEAC Computing Systems Week, Barcelona, Spain, May 2014. KW - Vehicle control platform KW - Software safety Y1 - 2014 ER - TY - CHAP A1 - Höfig, Kai T1 - Failure-dependent timing analysis-a new methodology for probabilistic worst-case execution time analysis T2 - International GI/ITG Conference on Measurement, Modelling, and Evaluation of Computing Systems and Dependability and Fault Tolerance. N2 - Embedded real-time systems are growing in complexity, which goes far beyond simplistic closed-loop functionality. Current approaches for worst-case execution time (WCET) analysis are used to verify the deadlines of such systems. These approaches calculate or measure the WCET as a single value that is expected as an upper bound for a system’s execution time. Overestimations are taken into account to make this upper bound a safe bound, but modern processor architectures expand those overestimations into unrealistic areas. Therefore, we present in this paper how of safety analysis model probabilities can be combined with elements of system development models to calculate a probabilistic WCET. This approach can be applied to systems that use mechanisms belonging to the area of fault tolerance, since such mechanisms are usually quantified using safety analyses to certify the system as being highly reliable or safe. A tool prototype implementing this approach is also presented which provides reliable safe upper bounds by performing a static WCET analysis and which overcomes the frequently encountered problem of dependence structures by using a fault injection approach. KW - Fault tolerance KW - Embedded real-time systems KW - Software safety KW - WCET Y1 - 2012 SP - 61 EP - 75 PB - Springer CY - Berlin, Heidelberg ER -