TY - JOUR A1 - Versen, Martin A1 - Ernst, W. T1 - Row hammer avoidance analysis of DDR3 SDRAM JF - Microelectronics Reliability N2 - A DDR3 SDRAM test setup implemented on the Griffin III test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests for different manufacturing technologies. The row hammer effect is depending on the number of stress activation cycles. The analysis is extended to an avoidance scheme with refreshes similar to the Target Row Refresh scheme for the DDR4 SDRAM technology. KW - DDR4 SDRAM technology Y1 - 2020 UR - https://doi.org/10.1016/j.microrel.2020.113744 SP - 113744 ER - TY - JOUR A1 - Versen, Martin A1 - Ernst, W. A1 - Gulati, P. T1 - A row hammer pattern analysis of DDR2 SDRAM JF - Microelectronics Reliability N2 - A DDR2 SDRAM test setup implemented on the Griffin III ATE test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests. The analysis confirms that the row hammer effect is caused by a charge excitation process depending on the number of stress activation cycles. The stress has to occur in the local neighborhood of the cells under test. Shallow impurity levels support the responsible charge carrier transport process in the used DDR2 SDRAM technology KW - Microelectronics KW - pattern analysis Y1 - 2018 UR - https://doi.org/10.1016/j.microrel.2017.07.022 VL - 76-77 SP - 64 EP - 67 ER -