TY - CHAP A1 - Dechant, Eduard A1 - Seliger, Norbert A1 - Kennel, Ralph T1 - Common Mode DGS EMI Filter Integrated into a GaN Half Bridge Switching Cell T2 - Procceedings International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (PCIM 2022) KW - EMI filter, DGS, GaN-HEMTs, Switching Cell Y1 - 2022 PB - Mesago ER - TY - CHAP A1 - Seliger, Norbert A1 - Dechant, Eduard A1 - Kennel, Ralph T1 - EMI mitigation by substrate integrated common mode filter T2 - Proceedings of 12th International Conference on Integrated Power Electronics Systems (CIPS 2022) KW - EMI filter, DGS, GaN-HEMTs Y1 - 2022 PB - VDE CY - Berlin (Germany) ER - TY - CHAP A1 - Dechant, Eduard A1 - Seliger, Norbert A1 - Kennel, Ralph T1 - Design of a Low Multi-Loop Inductance Three Level Neutral Point Clamped Converter with GaN HEMTs T2 - IEEE Energy Conversion Congress and Exposition (ECCE) N2 - This work shows a numerical and experimental analysis of a Neutral-Point-Clamp (NPC) three level inverter featuring an ultra low inductance printed circuit board (PCB) design in consideration of the mutual inductive and capacitive couplings. The commutation loops in this design are found to be strongly dependent on the vertical thickness of the used prepregs and the core. For vertical thicknesses ≤ 100 μm capacitive coupling must be taken into account in the switching cell design. Experimental measurements of a test set-up with a total PCB thickness of 400 μm results in commutation loop inductances from 1.4 nH up to 3.1 nH. In this set-up, switching tests without external gate resistor showed only a maximum voltage overshoot of 7% at 800 V. Based on a numerical analysis of the NPC cell we propose a further switching performance improvement with significant smaller parasitic inductance due to the application of novel printed circuit technologies such as the integration of bare dies into the printed circuit board or polyimide as an interlayer dielectric material. KW - Neutral-Point-Clamp (NPC) three level inverter KW - GaN HEMT KW - low multiloop inductance Y1 - 2020 PB - IEEE ER - TY - CHAP A1 - Hilverkus, Johannes A1 - Hagl, Rainer A1 - Kennel, Ralph T1 - Structural Mechanical Limitations of Dynamics of Servo Drives T2 - 25th International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM), Virtual Meeting KW - servo drives Y1 - 2020 SP - 11 EP - 16 ER - TY - CHAP A1 - Seliger, Norbert A1 - Dechant, Eduard A1 - Brendel, Christian A1 - Kennel, Ralph T1 - Reduction of Common Mode EMI noise in microstrip line based commutation paths designed for sub-nH loop inductance T2 - CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems, Berlin - Virtual Meeting N2 - We present a numerical and experimental design study for reducing conducted common mode noise for frequencies below 10MHz generated in switching cells comprising sub-nH commutation loops. Compared to conventional methods of adding external gate resistors our approach does not degrade efficiency. A parallel plate loop design (characterized by a minimum loop inductance and small board area usage) is found suboptimal in terms of conducted EMI compared to a micro-strip line loop geometry. The net ground impedance rather than the net ground inductance is found to mainly contribute to the observed EMI noise. KW - switching cell Y1 - 2020 ER - TY - CHAP A1 - Dechant, Eduard A1 - Seliger, Norbert A1 - Kennel, Ralph T1 - Performance of a GaN Half Bridge Switching Cell with Substrate Integrated Chips T2 - PCIM Europe 2019 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nürnberg N2 - Wide-bandgap semiconductors such as Silicon Carbide (SiC) or Gallium Nitride (GaN) enable fast switching and high switching frequencies of power electronics. However, this potential can not be exploited due to limitations caused by parasitic elements of packaging and interconnections. This paper shows a possibility to minimize parasitic elements of a half-bridge switching cell with 650 V GaN dies integrated into a printed circuit substrate. A sub-nH commutation loop of 0.5 nH inductance gives superior switching characteristics compared to circuits with packaged dies. Simulation and experimental results of an inverse double pulse test confirm our expectations. This study further reveals additional benefits of the proposed technology in terms of mechanical stability and thermal interfacing to heat sinks compared to circuits with packaged dies. KW - half bridge switching cell Y1 - 2019 ER - TY - JOUR A1 - Dechant, Eduard A1 - Seliger, Norbert A1 - Kennel, Ralph T1 - Power cycling and temperature endurance test of a GaN switching cell with substrate integrated chips JF - Microelectronics Reliability N2 - We present a reliability study of a half-bridge switching cell with substrate integrated 650 V GaN HEMTs. Power Cycling Testing with a ΔTj of 100 K has revealed thermo-mechanically induced failures of contact vias after more than 220 kcycles. The via failure mode of contact opening is confirmed by reverse-bias pulsed IV-measurements to be primarily triggered by a ΔTj imposed thermal gradient and not by a high Tj. The chip electrical characteristics, however, remained unaffected during Power Cycling. Furthermore, a High Temperature Storage test at 125 °C for 5000 h has shown no changes in the electrical performance of substrate integrated GaN HEMTs. KW - switching cell Y1 - 2019 UR - https://doi.org/10.1016/j.microrel.2019.06.064 VL - 100-101 SP - 113372 ER - TY - CHAP A1 - Dechant, Eduard A1 - Seliger, Norbert A1 - Kennel, Ralph T1 - A study of dielectric breakdown of a half-bridge switching cell with substrate integrated 650V GaN dies T2 - 2019 IEEE International Workshop on Integrated Power Packaging (IWIPP), Toulouse, France N2 - This paper proposes an ultra-low inductance half-bridge switching cell with substrate integrated 650V GaN bare dies. A vertical parallel-plate waveguide structure with 100 μm layer thickness results in a commutation loop inductance of 0.5 nH resulting in a negligible drain-source voltage overshoot in the inductive load standard pulse test. On the other hand reliable circuit operation requires an assessment of the isolation strength of the thin dielectric layer in the main commutation loop, because critical high local electric fields might occur between the pads. Measurements of the dielectric breakdown voltage followed by a statistical failure analysis provide a characteristic life of 14.7 kV and a 10% quantile of 13.5kV in the Weibull fitted data. This characteristic life depends strongly on the ambient temperature and drops to 4.1kV at 125°C. Additionally, ageing tests show an increasing in dielectric breakdown voltage after 500h, 1000h and 2000h at 125°C high-temperature storage due to resin densification processes. KW - half-bridge switching cell Y1 - 2019 UR - https://doi.org/10.1109/IWIPP.2019.8799104 ER - TY - CHAP A1 - Höllthaler, Julia A1 - Hagl, Rainer A1 - Kennel, Ralph T1 - Influence of the PWM Frequency on Dynamic and Position Stability of Servo Drives T2 - 25th International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM), Virtual Meeting N2 - The dynamic behavior and position stability of servo drives are influenced by many parameters. One major influencing parameter is the pulse width modulation (PWM) frequency. With inverters based on wide bandgap semiconductors, the PWM frequency can be increased. This enables a substantial increase in the current control bandwidth. The paper focuses on the influence of the PWM frequency on the dynamics of control loops and position stability, which are derived from theoretical correlations. The theory is verified using a test bench for high dynamic and position stability. The test bench is equipped with a voice coil motor and power electronic with gallium nitride (GaN) power semiconductors for switching frequencies of 100kHz and over. The achieved position stability, measured with a laser-based comparator at the tool center point, is lower than "+-1nm" with a standard deviation of "0.16nm" at a PWM frequency of "f_PWM=100kHz". KW - bandwidth Y1 - 2020 ER - TY - CHAP A1 - Höllthaler, Julia A1 - Hagl, Rainer A1 - Kennel, Ralph T1 - Bandwidth Improvements for Current Control Loops with a 100 kHz PWM Frequency and GaN Power Semiconductors T2 - 2019 58th Annual Conference of the Society of Instrument and Control Engineers of Japan (SICE), Hiroshima, Japan N2 - A discrete-time design method for a robust current controller of a servo drive has been developed. It takes the sampling time, the processing dead time and the dynamic behavior of the A/D converter into account. The theoretical calculations are verified using a test stand for high dynamics. The test stand includes a voice coil motor and power electronics with Gallium Nitride (GaN) power semiconductors for switching frequencies of more than 100 kHz. The bandwidth of the current control loop can be improved from typically 1 kHz to 1.5 kHz with insulated-gate bipolar transistor (IGBT) power semiconductors in state-of-the-art motion control systems to 10 kHz and more. KW - bandwidth KW - current control KW - servo drives KW - GaN power semiconductors KW - FPGA Y1 - 2019 UR - https://doi.org/10.23919/SICE.2019.8859873 ER -