<?xml version="1.0" encoding="utf-8"?>
<export-example>
  <doc>
    <id>1797</id>
    <completedYear>2012</completedYear>
    <publishedYear/>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>13.1</pageFirst>
    <pageLast/>
    <pageNumber>5</pageNumber>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName>VDE-VERLAG GMBH</publisherName>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>--</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Planar Interconnect Technology for Power Module System Integration</title>
    <abstract language="eng">The recent developments in power semiconductor devices and increasing demands on reliability as well as on operation performance require innovative package technologies. Such a novel package technique based on a Planar Interconnect Technology (SiPLIT®) for power modules is introduced in this work. This package features thick Cu interconnects on a high-reliable  insulating  film  for  power  semiconductor  chip  top  contacts.  Due  to  the  conductor  structure  and  contact  technology,  on-resistance  and  stray  inductances  are  very  low  compared  to  state-of-the-art  Al  wire  bonds.  In  addition,  large  area  contacting  improves  the  power  cycling  capability  and  surge  current  robustness  significantly.  These  remark-able  properties  have  been  verified  on  several  prototype  modules  where  the  manufacturing  process  has  also  been  optimised in terms of cost-effectiveness, system integration and maturity for series production.</abstract>
    <parentTitle language="eng">7th International Conference on Integrated Power Electronics Systems (CIPS)</parentTitle>
    <enrichment key="RS_Correlation">Nein</enrichment>
    <enrichment key="opus.source">publish</enrichment>
    <author>Karl Weidner</author>
    <author>Michael Kaspar</author>
    <author>Norbert Seliger</author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>planar interconnect technology</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>power module system integration</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>power semiconductor devices</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>reliability</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>innovative package</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>SiPLIT</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>power cycling capability</value>
    </subject>
    <collection role="institutes" number="">Fakultät für Ingenieurwissenschaften</collection>
    <thesisPublisher>Technische Hochschule Rosenheim</thesisPublisher>
  </doc>
</export-example>
