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  <doc>
    <id>667</id>
    <completedYear>2011</completedYear>
    <publishedYear/>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>bookpart</type>
    <publisherName>ASM International</publisherName>
    <publisherPlace>Ohio</publisherPlace>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2018-04-25</completedDate>
    <publishedDate>2018-06-04</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">DRAM Failure Analysis and Defect Localization Techniques, Microelectronics Failure Analysis</title>
    <abstract language="eng">Comprehensive guide to the process and test methods used for electronic device failure analysis. Contains dozens of articles—contributed by industry experts—covering a wide range of topics involving the failure analysis of microelectronics. It places the most important and up-to-date information on this subject at your fingertips. &#13;
Topic coverage includes: &#13;
Failure Analysis Process Flow&#13;
Failure Verification &#13;
Failure Modes and Failure Classification &#13;
Special Devices (MEMS, Optoelectronics, Passives) &#13;
Fault Localization Techniques: Package Level (NDT) &#13;
Die Level (Depackaging, Photon Emission, Microthermography, Laser-Based Methods, Particle Beam Methods) &#13;
Deprocessing &amp; Imaging Techniques: Deprocessing &#13;
General Imaging Techniques &#13;
Local Deprocessing &amp; Imaging &#13;
Circuit Edit and Design Modification &#13;
Material Analysis Techniques &#13;
Reference Information: Important Topics for Semiconductor Devices &#13;
Failure Analysis Techniques Roadmap &#13;
Failure Analysis Operations and Management &#13;
Appendices: Failure Analysis Terms, Definitions, and Acronyms &#13;
Industry Standards</abstract>
    <parentTitle language="eng">Desk Reference Sixth Edition</parentTitle>
    <enrichment key="review.accepted_by">2</enrichment>
    <author>Martin Versen</author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Microelectronics</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>DRAM Failure Analysis</value>
    </subject>
    <collection role="ddc" number="620">Ingenieurwissenschaften und zugeordnete Tätigkeiten</collection>
    <collection role="institutes" number="">Fakultät für Ingenieurwissenschaften</collection>
    <thesisPublisher>Technische Hochschule Rosenheim</thesisPublisher>
  </doc>
  <doc>
    <id>669</id>
    <completedYear>2011</completedYear>
    <publishedYear/>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2018-04-25</completedDate>
    <publishedDate>2018-06-04</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Worst Case Test Conditions for Defect Localization in DRAM Devices</title>
    <parentTitle language="eng">Microelectronics Seminar of the ISTFA 2011</parentTitle>
    <enrichment key="review.accepted_by">2</enrichment>
    <author>Martin Versen</author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>DRAM Devices</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Microelectronics</value>
    </subject>
    <collection role="ddc" number="620">Ingenieurwissenschaften und zugeordnete Tätigkeiten</collection>
    <collection role="institutes" number="">Fakultät für Ingenieurwissenschaften</collection>
    <thesisPublisher>Technische Hochschule Rosenheim</thesisPublisher>
  </doc>
  <doc>
    <id>665</id>
    <completedYear>2014</completedYear>
    <publishedYear/>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2018-04-25</completedDate>
    <publishedDate>2018-06-04</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Introduction to microcomputer technology with the MSP430 Launch Pad in remote labs</title>
    <abstract language="eng">Texas Instruments' MSP430 Launch Pad is used as a key component for remote labs that complement an introduction course to microcomputer technology in the bachelor program Mechatronic at the University of Applied Sciences in Rosenheim. The remote labs use breakout boards and include a timer experiment with generation of pulse width modulation signals, I2C communication and analog to digital conversion.</abstract>
    <parentTitle language="eng">Global Engineering Education Conference (EDUCON), 2014 IEEE</parentTitle>
    <enrichment key="review.accepted_by">2</enrichment>
    <author>Martin Versen</author>
    <author>S. Kipfelsberger</author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Microelectronics</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Microcomputer</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>MSP430 Launch Pad</value>
    </subject>
    <collection role="ddc" number="620">Ingenieurwissenschaften und zugeordnete Tätigkeiten</collection>
    <collection role="institutes" number="">Fakultät für Ingenieurwissenschaften</collection>
    <thesisPublisher>Technische Hochschule Rosenheim</thesisPublisher>
  </doc>
  <doc>
    <id>664</id>
    <completedYear>2014</completedYear>
    <publishedYear/>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2018-04-25</completedDate>
    <publishedDate>2018-06-04</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Introduction to Verification and Test Using a 4-Bit Arithmetic Logic Unit Including a Failure Module in a Xilinx XC9572XL CPLD</title>
    <parentTitle language="eng">Proceedings of the 40th ISTFA 2014</parentTitle>
    <enrichment key="review.accepted_by">2</enrichment>
    <author>Martin Versen</author>
    <author>M. Hayn</author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Microelectronics</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Xilinx XC9572XL CPLD</value>
    </subject>
    <collection role="ddc" number="620">Ingenieurwissenschaften und zugeordnete Tätigkeiten</collection>
    <collection role="institutes" number="">Fakultät für Ingenieurwissenschaften</collection>
    <thesisPublisher>Technische Hochschule Rosenheim</thesisPublisher>
  </doc>
  <doc>
    <id>661</id>
    <completedYear>2017</completedYear>
    <publishedYear/>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>64</pageFirst>
    <pageLast>67</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume>76-77</volume>
    <type>article</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2018-04-25</completedDate>
    <publishedDate>2018-06-04</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">A row hammer pattern analysis of DDR2 SDRAM</title>
    <abstract language="eng">A DDR2 SDRAM test setup implemented on the Griffin III ATE test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests. &#13;
The analysis confirms that the row hammer effect is caused by a charge excitation process depending on the number of stress activation cycles. The stress has to occur in the local neighborhood of the cells under test. &#13;
Shallow impurity levels support the responsible charge carrier transport process in the used DDR2 SDRAM technology</abstract>
    <parentTitle language="eng">Microelectronics Reliability</parentTitle>
    <identifier type="url">https://doi.org/10.1016/j.microrel.2017.07.022</identifier>
    <enrichment key="PeerReviewed">Ja</enrichment>
    <author>Martin Versen</author>
    <author>W. Ernst</author>
    <author>P. Gulati</author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Microelectronics</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>pattern analysis</value>
    </subject>
    <collection role="ddc" number="620">Ingenieurwissenschaften und zugeordnete Tätigkeiten</collection>
    <collection role="institutes" number="">Fakultät für Ingenieurwissenschaften</collection>
    <thesisPublisher>Technische Hochschule Rosenheim</thesisPublisher>
  </doc>
  <doc>
    <id>663</id>
    <completedYear>2015</completedYear>
    <publishedYear/>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>contributiontoperiodical</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2018-04-25</completedDate>
    <publishedDate>2018-06-04</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Test setup for reliability studies of DDR2 SDRAM</title>
    <abstract language="eng">A DDR2 DRAM test setup is developed and implemented on the Griffin III ATE test system from HILEVEL Technologies. The test system provides a raw platform for performing various mixed signal and digital tests. In order to configure patterns easily in a vector format, a software platform is developed to manage test patterns according to the user's analysis needs. As examples, retention test patterns with disabled self-refresh are applied to 2 Gbit DDR2 SDRAM of two different DRAM vendors. The devices are characterized in respect to their intrinsic leakage and data retention behavior under the influence of stress conditions such as temperature or access algorithm. The tests are automated and test data is logged for an off-line data analysis. Data is recorded before and after solder simulation steps in order to observe a retention time degradation.</abstract>
    <parentTitle language="eng">Microelectronics Reliability</parentTitle>
    <enrichment key="review.accepted_by">2</enrichment>
    <author>Martin Versen</author>
    <author>W. Ernst</author>
    <author>P. Gulati</author>
    <author>G. Singh</author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Microelectronics</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>DRAM retention solder simulation</value>
    </subject>
    <collection role="ddc" number="620">Ingenieurwissenschaften und zugeordnete Tätigkeiten</collection>
    <collection role="institutes" number="">Fakultät für Ingenieurwissenschaften</collection>
    <thesisPublisher>Technische Hochschule Rosenheim</thesisPublisher>
  </doc>
</export-example>
