@inproceedings{HoellthalerHaglKennel2020, author = {H{\"o}llthaler, Julia and Hagl, Rainer and Kennel, Ralph}, title = {Influence of the PWM Frequency on Dynamic and Position Stability of Servo Drives}, series = {25th International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM), Virtual Meeting}, booktitle = {25th International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM), Virtual Meeting}, year = {2020}, abstract = {The dynamic behavior and position stability of servo drives are influenced by many parameters. One major influencing parameter is the pulse width modulation (PWM) frequency. With inverters based on wide bandgap semiconductors, the PWM frequency can be increased. This enables a substantial increase in the current control bandwidth. The paper focuses on the influence of the PWM frequency on the dynamics of control loops and position stability, which are derived from theoretical correlations. The theory is verified using a test bench for high dynamic and position stability. The test bench is equipped with a voice coil motor and power electronic with gallium nitride (GaN) power semiconductors for switching frequencies of 100kHz and over. The achieved position stability, measured with a laser-based comparator at the tool center point, is lower than "+-1nm" with a standard deviation of "0.16nm" at a PWM frequency of "f_PWM=100kHz".}, language = {en} } @inproceedings{SeligerDechantBrendeletal.2020, author = {Seliger, Norbert and Dechant, Eduard and Brendel, Christian and Kennel, Ralph}, title = {Reduction of Common Mode EMI noise in microstrip line based commutation paths designed for sub-nH loop inductance}, series = {CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems, Berlin - Virtual Meeting}, booktitle = {CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems, Berlin - Virtual Meeting}, pages = {6}, year = {2020}, abstract = {We present a numerical and experimental design study for reducing conducted common mode noise for frequencies below 10MHz generated in switching cells comprising sub-nH commutation loops. Compared to conventional methods of adding external gate resistors our approach does not degrade efficiency. A parallel plate loop design (characterized by a minimum loop inductance and small board area usage) is found suboptimal in terms of conducted EMI compared to a micro-strip line loop geometry. The net ground impedance rather than the net ground inductance is found to mainly contribute to the observed EMI noise.}, language = {en} } @inproceedings{HilverkusHaglKennel2020, author = {Hilverkus, Johannes and Hagl, Rainer and Kennel, Ralph}, title = {Structural Mechanical Limitations of Dynamics of Servo Drives}, series = {25th International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM), Virtual Meeting}, booktitle = {25th International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM), Virtual Meeting}, pages = {11 -- 16}, year = {2020}, language = {en} } @inproceedings{VersenKipfelsbergerBernhardt2020, author = {Versen, Martin and Kipfelsberger, Stefan and Bernhardt, Andreas}, title = {Einf{\"u}hrung in die Aufbau- und Verbindungstechnik durch eine interaktive und praxisnahe Qualifizierung in der Leiterplattentechnik}, series = {Tagungsband 2. Symposium Elektronik und Systemintegration ESI 2020: "Intelligente Systeme und ihre Komponenten: Forschung und industrielle Anwendung"}, booktitle = {Tagungsband 2. Symposium Elektronik und Systemintegration ESI 2020: "Intelligente Systeme und ihre Komponenten: Forschung und industrielle Anwendung"}, address = {Landshut}, isbn = {978-3-9818439-4-1}, pages = {54 -- 62}, year = {2020}, abstract = {F{\"u}r eine Einf{\"u}hrung in die fertigungstechnischen Grundlagen der Aufbau- und Verbindungstechnik sind im Wahlfach „Leiterplattentechnik Praktikum" an der Technischen Hochschule (TH) Rosenheim Inhalte der Prozesstechnik und des Leiterplattendesigns miteinander kombiniert. Zu Beginn der Veranstaltung zeichnen die Praktikumsteilnehmer ein Layout f{\"u}r eine Leiterbahn-Teststruktur, welche anschließend im Haus gefertigt wird. Nach der Fertigung folgt eine elektrische und optische Charakterisierung zur Kontrolle der Prozessqualit{\"a}t. Die praxisnahe Erstellung eines einlagigen Layouts f{\"u}r eine LED-Taschenlampe auf Basis eines vorgegebenen Schaltplans und innerhalb einer begrenzten Platinenfl{\"a}che sowie dessen Fertigung bef{\"a}higen die Kursteilnehmer sp{\"a}ter, eigene Layouts f{\"u}r elektronische Schaltungen selbstst{\"a}ndig zu entwickeln. Die anspruchsvolle, teilautomatische Best{\"u}ckung einer zweilagigen, vorgegebenen SMT(Surface Mount Technology)-Leiterplatte, die ein FM-Radio mit Capacitive Touch-Steuerung bildet, rundet die erfolgreiche Qualifizierung in der Leiterplattentechnik ab.}, language = {de} } @inproceedings{WohlschlaegerHolstVersen2020, author = {Wohlschl{\"a}ger, Maximilian and Holst, Gerhard and Versen, Martin}, title = {Automatische Erkennung von Kunststoffen durch bildgebende Fluoreszenzabklingzeitmessung}, series = {Tagungsband: AALE 2020 - Automatisierung und Mensch-Technik-Interaktion 17. Fachkonferenz}, booktitle = {Tagungsband: AALE 2020 - Automatisierung und Mensch-Technik-Interaktion 17. Fachkonferenz}, publisher = {VDE Verlag Berlin}, isbn = {978-3-8007-5180-8}, pages = {223 -- 231}, year = {2020}, language = {de} } @inproceedings{HeitauerVersen2020, author = {Heitauer, Mathias and Versen, Martin}, title = {Co-Simulation eines zweistufigen Operationsverst{\"a}rkers mit MATLAB/Simulink und Cadence ADE}, series = {Tagungsband: AALE 2020 - Automatisierung und Mensch-Technik-Interaktion 17. Fachkonferenz}, booktitle = {Tagungsband: AALE 2020 - Automatisierung und Mensch-Technik-Interaktion 17. Fachkonferenz}, publisher = {VDE Verlag Berlin}, address = {Berlin}, isbn = {978-3-8007-5180-8}, pages = {287 -- 291}, year = {2020}, abstract = {Ein zweistufiger Operationsverst{\"a}rker wird parallel in einer 180nm CMOS Technologie in der Entwicklungsumgebung von Cadence ADE und in MATLAB/Simulink in einem modellbasierten Ansatz entworfen und simuliert. F{\"u}r den Entwurf in MATLAB/Simulink wird das Kleinsignalersatzschaltbild der physikalischen Schaltung verwendet. Mit Hilfe der Co-Simulation zwischen Cadence und MATLAB/Simulink wird das Verhalten simuliert und ausgewertet. Die Ergebnisse aus beiden Modellen stimmen {\"u}berein, wodurch festgestellt werden kann, dass die Co-Simulation erfolgreich war.}, language = {de} } @inproceedings{WohlschlaegerHolstVersen2020, author = {Wohlschl{\"a}ger, Maximilian and Holst, G. and Versen, Martin}, title = {A novel approach to optically distinguish plastics based on fluorescence lifetime measurements}, series = {2020 IEEE Sensors Applications Symposium (SAS), Kuala Lumpur, Malaysia}, booktitle = {2020 IEEE Sensors Applications Symposium (SAS), Kuala Lumpur, Malaysia}, pages = {1 -- 6}, year = {2020}, language = {en} } @article{WohlschlaegerVersen2020, author = {Wohlschl{\"a}ger, Maximilian and Versen, Martin}, title = {Detection of plastics in water based on their fluorescence behavior}, series = {Journal of Sensors and Sensor Systems}, volume = {9}, journal = {Journal of Sensors and Sensor Systems}, number = {2}, pages = {337 -- 343}, year = {2020}, abstract = {Plastic waste is one of the biggest growing factors contributing to environmental pollution. So far there has been no established method to detect and identify plastics in environmental matrices. Thus, a method based on their characteristic fluorescence behavior is used to investigate whether plastics can be detected and identified in tap water under laboratory conditions. The experiments show that the identification of plastics as a function of water depth is possible. As the identification becomes more difficult with higher water depths, investigations with a highly sensitive imaging method were carried out to obtain an areal integration of the fluorescent light and thus better results.}, language = {en} } @article{VersenErnst2020, author = {Versen, Martin and Ernst, W.}, title = {Row hammer avoidance analysis of DDR3 SDRAM}, series = {Microelectronics Reliability}, journal = {Microelectronics Reliability}, pages = {113744}, year = {2020}, abstract = {A DDR3 SDRAM test setup implemented on the Griffin III test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests for different manufacturing technologies. The row hammer effect is depending on the number of stress activation cycles. The analysis is extended to an avoidance scheme with refreshes similar to the Target Row Refresh scheme for the DDR4 SDRAM technology.}, language = {en} } @inproceedings{DechantSeligerKennel2020, author = {Dechant, Eduard and Seliger, Norbert and Kennel, Ralph}, title = {Design of a Low Multi-Loop Inductance Three Level Neutral Point Clamped Converter with GaN HEMTs}, series = {IEEE Energy Conversion Congress and Exposition (ECCE)}, booktitle = {IEEE Energy Conversion Congress and Exposition (ECCE)}, publisher = {IEEE}, pages = {6}, year = {2020}, abstract = {This work shows a numerical and experimental analysis of a Neutral-Point-Clamp (NPC) three level inverter featuring an ultra low inductance printed circuit board (PCB) design in consideration of the mutual inductive and capacitive couplings. The commutation loops in this design are found to be strongly dependent on the vertical thickness of the used prepregs and the core. For vertical thicknesses ≤ 100 μm capacitive coupling must be taken into account in the switching cell design. Experimental measurements of a test set-up with a total PCB thickness of 400 μm results in commutation loop inductances from 1.4 nH up to 3.1 nH. In this set-up, switching tests without external gate resistor showed only a maximum voltage overshoot of 7\% at 800 V. Based on a numerical analysis of the NPC cell we propose a further switching performance improvement with significant smaller parasitic inductance due to the application of novel printed circuit technologies such as the integration of bare dies into the printed circuit board or polyimide as an interlayer dielectric material.}, language = {en} }