@techreport{BarthBeneckenBetzetal.2016, author = {Barth, Simon and Benecken, Gerd and Betz, Andreas and Binninger, Karsten and Graule, Verena and Hack, Andreas and Haegele, Rainer and Hartmann, Markus and Hauck-Bauer, Eva and Haut, Sandra and J{\"a}ger, Johannes and Kagerl, Andreas and Karlinger, Peter and Konle, Elke and K{\"o}ster, Heinrich and Krause, Harald and Krommes, Sandra and Meissner, Thomas and Michanickl, Andreas and Sandor, Viktor and Schanda, Ulrich and Schemme, Michael and Sebald, Daniela and Spindler, Uli and Stauss, Kilian and Strobl, Thomas and Sussmann, Monika and Versen, Martin and Voit, Johann and Wambsganß, Mathias and Wellisch, Ulrich and Zauner, Johannes}, title = {Forschungsbericht 2015}, organization = {Hochschule Rosenheim}, url = {http://nbn-resolving.de/urn:nbn:de:bvb:861-opus4-12304}, pages = {76}, year = {2016}, abstract = {Mit dem j{\"a}hrlich erscheinenden Forschungsbericht m{\"o}chte die Hochschule Rosenheim einen Einblick in ihre vielf{\"a}ltigen Projekte und Aktivit{\"a}ten der angewandten Forschung und Entwicklung geben. Im Forschungsbericht 2015 wird {\"u}ber Vorhaben im Jahr 2015 berichtet.}, language = {de} } @inproceedings{VersenKipfelsbergerSoekmen2016, author = {Versen, Martin and Kipfelsberger, F. and Soekmen, F.}, title = {Model-Based Reference Design Projects with MathWorks' HDL Workflow Advisor for Custom-Specific Electronics with the Zedboard}, series = {ANALOG 2016; 15. ITG/GMM-Symposium, Bremen, Germany}, booktitle = {ANALOG 2016; 15. ITG/GMM-Symposium, Bremen, Germany}, year = {2016}, abstract = {Reference design projects are implemented to the Xilinx Zynq on the Zedboard which is extended by user defined electronic hardware connected through the Zedboard's FMC (FPGA Mezzanine Card) connector. The implementation method with HDL Workflow Advisor includes constraint definitions for modified reference design projects for use with digital input and outputs and Zynq's XADC (Analog-Digital converter) which is characterized and compared to its data sheet. The bandwidth of the Zynq's internal AXI (Advanced eXtensible Interface) bus connected to the Simulink host PC is determined.}, language = {en} }