@article{VersenErnstGulati2017, author = {Versen, Martin and Ernst, W. and Gulati, P.}, title = {A row hammer pattern analysis of DDR2 SDRAM}, series = {Microelectronics Reliability}, volume = {76-77}, journal = {Microelectronics Reliability}, pages = {64 -- 67}, year = {2017}, abstract = {A DDR2 SDRAM test setup implemented on the Griffin III ATE test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests. The analysis confirms that the row hammer effect is caused by a charge excitation process depending on the number of stress activation cycles. The stress has to occur in the local neighborhood of the cells under test. Shallow impurity levels support the responsible charge carrier transport process in the used DDR2 SDRAM technology}, language = {en} } @article{VersenErnstGulatietal.2015, author = {Versen, Martin and Ernst, W. and Gulati, P. and Singh, G.}, title = {Test setup for reliability studies of DDR2 SDRAM}, series = {Microelectronics Reliability}, journal = {Microelectronics Reliability}, year = {2015}, abstract = {A DDR2 DRAM test setup is developed and implemented on the Griffin III ATE test system from HILEVEL Technologies. The test system provides a raw platform for performing various mixed signal and digital tests. In order to configure patterns easily in a vector format, a software platform is developed to manage test patterns according to the user's analysis needs. As examples, retention test patterns with disabled self-refresh are applied to 2 Gbit DDR2 SDRAM of two different DRAM vendors. The devices are characterized in respect to their intrinsic leakage and data retention behavior under the influence of stress conditions such as temperature or access algorithm. The tests are automated and test data is logged for an off-line data analysis. Data is recorded before and after solder simulation steps in order to observe a retention time degradation.}, language = {en} } @article{VersenErnst2020, author = {Versen, Martin and Ernst, W.}, title = {Row hammer avoidance analysis of DDR3 SDRAM}, series = {Microelectronics Reliability}, journal = {Microelectronics Reliability}, pages = {113744}, year = {2020}, abstract = {A DDR3 SDRAM test setup implemented on the Griffin III test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests for different manufacturing technologies. The row hammer effect is depending on the number of stress activation cycles. The analysis is extended to an avoidance scheme with refreshes similar to the Target Row Refresh scheme for the DDR4 SDRAM technology.}, language = {en} }