@incollection{Versen2011, author = {Versen, Martin}, title = {DRAM Failure Analysis and Defect Localization Techniques, Microelectronics Failure Analysis}, series = {Desk Reference Sixth Edition}, booktitle = {Desk Reference Sixth Edition}, publisher = {ASM International}, address = {Ohio}, publisher = {Technische Hochschule Rosenheim}, year = {2011}, abstract = {Comprehensive guide to the process and test methods used for electronic device failure analysis. Contains dozens of articles—contributed by industry experts—covering a wide range of topics involving the failure analysis of microelectronics. It places the most important and up-to-date information on this subject at your fingertips.  Topic coverage includes:  Failure Analysis Process Flow Failure Verification  Failure Modes and Failure Classification  Special Devices (MEMS, Optoelectronics, Passives)  Fault Localization Techniques: Package Level (NDT)  Die Level (Depackaging, Photon Emission, Microthermography, Laser-Based Methods, Particle Beam Methods)  Deprocessing \& Imaging Techniques: Deprocessing  General Imaging Techniques  Local Deprocessing \& Imaging  Circuit Edit and Design Modification  Material Analysis Techniques  Reference Information: Important Topics for Semiconductor Devices  Failure Analysis Techniques Roadmap  Failure Analysis Operations and Management  Appendices: Failure Analysis Terms, Definitions, and Acronyms  Industry Standards}, language = {en} } @inproceedings{Versen2011, author = {Versen, Martin}, title = {Worst Case Test Conditions for Defect Localization in DRAM Devices}, series = {Microelectronics Seminar of the ISTFA 2011}, booktitle = {Microelectronics Seminar of the ISTFA 2011}, year = {2011}, language = {en} } @inproceedings{VersenKipfelsberger2014, author = {Versen, Martin and Kipfelsberger, S.}, title = {Introduction to microcomputer technology with the MSP430 Launch Pad in remote labs}, series = {Global Engineering Education Conference (EDUCON), 2014 IEEE}, booktitle = {Global Engineering Education Conference (EDUCON), 2014 IEEE}, year = {2014}, abstract = {Texas Instruments' MSP430 Launch Pad is used as a key component for remote labs that complement an introduction course to microcomputer technology in the bachelor program Mechatronic at the University of Applied Sciences in Rosenheim. The remote labs use breakout boards and include a timer experiment with generation of pulse width modulation signals, I2C communication and analog to digital conversion.}, language = {en} } @inproceedings{VersenHayn2014, author = {Versen, Martin and Hayn, M.}, title = {Introduction to Verification and Test Using a 4-Bit Arithmetic Logic Unit Including a Failure Module in a Xilinx XC9572XL CPLD}, series = {Proceedings of the 40th ISTFA 2014}, booktitle = {Proceedings of the 40th ISTFA 2014}, year = {2014}, language = {en} } @article{VersenErnstGulati2017, author = {Versen, Martin and Ernst, W. and Gulati, P.}, title = {A row hammer pattern analysis of DDR2 SDRAM}, series = {Microelectronics Reliability}, volume = {76-77}, journal = {Microelectronics Reliability}, pages = {64 -- 67}, year = {2017}, abstract = {A DDR2 SDRAM test setup implemented on the Griffin III ATE test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests. The analysis confirms that the row hammer effect is caused by a charge excitation process depending on the number of stress activation cycles. The stress has to occur in the local neighborhood of the cells under test. Shallow impurity levels support the responsible charge carrier transport process in the used DDR2 SDRAM technology}, language = {en} } @article{VersenErnstGulatietal.2015, author = {Versen, Martin and Ernst, W. and Gulati, P. and Singh, G.}, title = {Test setup for reliability studies of DDR2 SDRAM}, series = {Microelectronics Reliability}, journal = {Microelectronics Reliability}, year = {2015}, abstract = {A DDR2 DRAM test setup is developed and implemented on the Griffin III ATE test system from HILEVEL Technologies. The test system provides a raw platform for performing various mixed signal and digital tests. In order to configure patterns easily in a vector format, a software platform is developed to manage test patterns according to the user's analysis needs. As examples, retention test patterns with disabled self-refresh are applied to 2 Gbit DDR2 SDRAM of two different DRAM vendors. The devices are characterized in respect to their intrinsic leakage and data retention behavior under the influence of stress conditions such as temperature or access algorithm. The tests are automated and test data is logged for an off-line data analysis. Data is recorded before and after solder simulation steps in order to observe a retention time degradation.}, language = {en} }