@article{SladeShur1998, author = {Slade, Holly C. and Shur, M.S.}, title = {Analysis of bias stress on unpassivated hydrogenated amorphous silicon thin-film transistors}, series = {IEEE Transactions on Electron Devices}, volume = {45}, journal = {IEEE Transactions on Electron Devices}, number = {7}, pages = {1548 -- 1553}, year = {1998}, abstract = {Both the subthreshold slope and the threshold voltage in inverted-staggered amorphous silicon thin-film transistors (a-Si:H TFTs) are vulnerable to metastable changes in the density of states (DOS) due to Fermi level displacement. In previous work, we have used passivated and unpassivated TFTs to distinguish between the effects of bulk states and interface states at the top passivating nitride interface. Here we report the results of experimental measurements and two-dimensional (2-D) simulations on unpassivated TFTs. Since there are no top interface states, all the observed changes are due solely to the bulk DOS. The subthreshold current activation energies in a-Si:H TFTs are compared for n-channel nonpassivated TFTs before and after bias stress. The experimental results agree well with the 2-D simulations, confirming that the dependence of subthreshold current activation energy on gate bias reveals the distribution of the DOS in energy but cannot resolve the magnitude of features in the DOS. This type of analysis is not accurate for TFTs with a top passivating nitride, since the activation energies in such devices are affected by the interfere states.}, language = {en} } @article{SladeShurDeaneetal.1996, author = {Slade, Holly C. and Shur, M.S. and Deane, S.C. and Hack, M.}, title = {Below threshold conduction in a-Si:H thin film transistors with and without a silicon nitride passivating layer}, series = {Applied Physics Letters}, volume = {69}, journal = {Applied Physics Letters}, number = {17}, pages = {2560}, year = {1996}, abstract = {We report temperature measurements of inverted staggered amorphous silicon thin film transistor subthreshold conductance for devices with and without a top silicon nitride passivating layer. Subthreshold conductance activation energies clearly show the different conductance paths in the active layer of these devices. Transistors with no top nitride layer conduct in the bulk amorphous silicon, whereas the devices with a top nitride layer conduct at the interface between the amorphous silicon and the top nitride (a ''back'' channel). Gate bias stressing and light soaking experiments uphold the existence of the back channel. We also present two-dimensional simulations that support our interpretation of the experimental data.}, language = {en} }