@misc{EffenbergerStubenrauchDechantetal.2025, author = {Effenberger, Thomas and Stubenrauch, Franz and Dechant, Eduard and Heldwein, Marcelo Lobo}, title = {Resonances and Oscillations in DC Grids}, series = {PCIM Conference 2025}, journal = {PCIM Conference 2025}, doi = {10.30420/566541322}, pages = {8}, year = {2025}, abstract = {A trend has been emerging in the field of industrial automation: direct current (DC) is making a comeback. This is due to the desire for greater energy efficiency and flexible, intelligent energy distribution. However, DC can still exhibit alternating current (AC) components from pulsating loads on an industrial grid, which may excite resonances. This work derives an equivalent circuit model for the grid and verifies it using a motor test bench. Design considerations for the DC link capacitance are presented to enable the integration into a decentralized drive.}, language = {en} } @phdthesis{Dechant2022, author = {Dechant, Eduard}, title = {Aufbau- und Verbindungstechniken auf Basis von Leiterplattentechnologien f{\"u}r WBG-Leistungstransistoren}, school = {Technische Hochschule Rosenheim}, year = {2022}, abstract = {Diese Arbeit untersucht Aufbau- und Verbindungstechniken auf Basis von Leiterplattentechnologien f{\"u}r Wide-Bandgap-Leistungstransistoren mit schnellen Schaltvorg{\"a}ngen. Mit dem Ziel ein {\"u}berschwingungsfreies Schalten zu erreichen, werden niederinduktive Konzepte f{\"u}r Zweilevel- und Dreilevel-Inverter im Hinblick auf verschiedene Schichtdicken bzw. Leiterplattentechnologien vorgestellt und diskutiert. Dabei konnte gezeigt werden, dass Schaltzellen unter Ber{\"u}cksichtigung von parasit{\"a}ren Kapazit{\"a}ten so niederinduktiv gestaltet werden k{\"o}nnen, dass ein {\"U}berschwingen beim Schaltvorgang keine Limitierung mehr darstellt. Neuartige Aufbau- und Verbindungstechniken, wie die Integration der Halbleiter in den Kern der Leiterplatte, k{\"o}nnen zudem die elektrischen, thermischen und mechanischen Eigenschaften im Vergleich zu konventionellen Bauelementen verbessern. D{\"u}nnfilmtechnologien zeigen eine bessere St{\"o}rfestigkeit bzw. ein geringeres {\"U}bersprechen auf andere Signalleitungen. Außerdem wurden Filtermaßnahmen zur Reduzierung von hochfrequenten St{\"o}rspannungen, die durch kurze Schaltzeiten entstehen, untersucht.}, language = {de} } @inproceedings{DechantSeligerKennel2022, author = {Dechant, Eduard and Seliger, Norbert and Kennel, Ralph}, title = {Common Mode DGS EMI Filter Integrated into a GaN Half Bridge Switching Cell}, series = {Procceedings International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (PCIM 2022)}, booktitle = {Procceedings International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (PCIM 2022)}, publisher = {Mesago}, organization = {Labor f{\"u}r Leistungselektronik und EMV, TH Rosenheim}, pages = {6}, year = {2022}, language = {en} } @inproceedings{SeligerDechantKennel2022, author = {Seliger, Norbert and Dechant, Eduard and Kennel, Ralph}, title = {EMI mitigation by substrate integrated common mode filter}, series = {Proceedings of 12th International Conference on Integrated Power Electronics Systems (CIPS 2022)}, booktitle = {Proceedings of 12th International Conference on Integrated Power Electronics Systems (CIPS 2022)}, publisher = {VDE}, address = {Berlin (Germany)}, organization = {Labor f{\"u}r Leistungselektronik und EMV, TH Rosenheim}, year = {2022}, language = {en} } @inproceedings{DechantSeligerKennel2020, author = {Dechant, Eduard and Seliger, Norbert and Kennel, Ralph}, title = {Design of a Low Multi-Loop Inductance Three Level Neutral Point Clamped Converter with GaN HEMTs}, series = {IEEE Energy Conversion Congress and Exposition (ECCE)}, booktitle = {IEEE Energy Conversion Congress and Exposition (ECCE)}, publisher = {IEEE}, pages = {6}, year = {2020}, abstract = {This work shows a numerical and experimental analysis of a Neutral-Point-Clamp (NPC) three level inverter featuring an ultra low inductance printed circuit board (PCB) design in consideration of the mutual inductive and capacitive couplings. The commutation loops in this design are found to be strongly dependent on the vertical thickness of the used prepregs and the core. For vertical thicknesses ≤ 100 μm capacitive coupling must be taken into account in the switching cell design. Experimental measurements of a test set-up with a total PCB thickness of 400 μm results in commutation loop inductances from 1.4 nH up to 3.1 nH. In this set-up, switching tests without external gate resistor showed only a maximum voltage overshoot of 7\% at 800 V. Based on a numerical analysis of the NPC cell we propose a further switching performance improvement with significant smaller parasitic inductance due to the application of novel printed circuit technologies such as the integration of bare dies into the printed circuit board or polyimide as an interlayer dielectric material.}, language = {en} } @inproceedings{SeligerDechantBrendeletal.2020, author = {Seliger, Norbert and Dechant, Eduard and Brendel, Christian and Kennel, Ralph}, title = {Reduction of Common Mode EMI noise in microstrip line based commutation paths designed for sub-nH loop inductance}, series = {CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems, Berlin - Virtual Meeting}, booktitle = {CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems, Berlin - Virtual Meeting}, pages = {6}, year = {2020}, abstract = {We present a numerical and experimental design study for reducing conducted common mode noise for frequencies below 10MHz generated in switching cells comprising sub-nH commutation loops. Compared to conventional methods of adding external gate resistors our approach does not degrade efficiency. A parallel plate loop design (characterized by a minimum loop inductance and small board area usage) is found suboptimal in terms of conducted EMI compared to a micro-strip line loop geometry. The net ground impedance rather than the net ground inductance is found to mainly contribute to the observed EMI noise.}, language = {en} } @inproceedings{DechantSeligerKennel2019, author = {Dechant, Eduard and Seliger, Norbert and Kennel, Ralph}, title = {Performance of a GaN Half Bridge Switching Cell with Substrate Integrated Chips}, series = {PCIM Europe 2019 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, N{\"u}rnberg}, booktitle = {PCIM Europe 2019 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, N{\"u}rnberg}, pages = {7}, year = {2019}, abstract = {Wide-bandgap semiconductors such as Silicon Carbide (SiC) or Gallium Nitride (GaN) enable fast switching and high switching frequencies of power electronics. However, this potential can not be exploited due to limitations caused by parasitic elements of packaging and interconnections. This paper shows a possibility to minimize parasitic elements of a half-bridge switching cell with 650 V GaN dies integrated into a printed circuit substrate. A sub-nH commutation loop of 0.5 nH inductance gives superior switching characteristics compared to circuits with packaged dies. Simulation and experimental results of an inverse double pulse test confirm our expectations. This study further reveals additional benefits of the proposed technology in terms of mechanical stability and thermal interfacing to heat sinks compared to circuits with packaged dies.}, language = {en} } @article{DechantSeligerKennel2019, author = {Dechant, Eduard and Seliger, Norbert and Kennel, Ralph}, title = {Power cycling and temperature endurance test of a GaN switching cell with substrate integrated chips}, series = {Microelectronics Reliability}, volume = {100-101}, journal = {Microelectronics Reliability}, pages = {113372}, year = {2019}, abstract = {We present a reliability study of a half-bridge switching cell with substrate integrated 650 V GaN HEMTs. Power Cycling Testing with a ΔTj of 100 K has revealed thermo-mechanically induced failures of contact vias after more than 220 kcycles. The via failure mode of contact opening is confirmed by reverse-bias pulsed IV-measurements to be primarily triggered by a ΔTj imposed thermal gradient and not by a high Tj. The chip electrical characteristics, however, remained unaffected during Power Cycling. Furthermore, a High Temperature Storage test at 125 °C for 5000 h has shown no changes in the electrical performance of substrate integrated GaN HEMTs.}, language = {en} } @inproceedings{DechantSeligerKennel2019, author = {Dechant, Eduard and Seliger, Norbert and Kennel, Ralph}, title = {A study of dielectric breakdown of a half-bridge switching cell with substrate integrated 650V GaN dies}, series = {2019 IEEE International Workshop on Integrated Power Packaging (IWIPP), Toulouse, France}, booktitle = {2019 IEEE International Workshop on Integrated Power Packaging (IWIPP), Toulouse, France}, year = {2019}, abstract = {This paper proposes an ultra-low inductance half-bridge switching cell with substrate integrated 650V GaN bare dies. A vertical parallel-plate waveguide structure with 100 μm layer thickness results in a commutation loop inductance of 0.5 nH resulting in a negligible drain-source voltage overshoot in the inductive load standard pulse test. On the other hand reliable circuit operation requires an assessment of the isolation strength of the thin dielectric layer in the main commutation loop, because critical high local electric fields might occur between the pads. Measurements of the dielectric breakdown voltage followed by a statistical failure analysis provide a characteristic life of 14.7 kV and a 10\% quantile of 13.5kV in the Weibull fitted data. This characteristic life depends strongly on the ambient temperature and drops to 4.1kV at 125°C. Additionally, ageing tests show an increasing in dielectric breakdown voltage after 500h, 1000h and 2000h at 125°C high-temperature storage due to resin densification processes.}, language = {en} }