@inproceedings{SeligerDechantBrendeletal.2020, author = {Seliger, Norbert and Dechant, Eduard and Brendel, Christian and Kennel, Ralph}, title = {Reduction of Common Mode EMI noise in microstrip line based commutation paths designed for sub-nH loop inductance}, series = {CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems, Berlin - Virtual Meeting}, booktitle = {CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems, Berlin - Virtual Meeting}, pages = {6}, year = {2020}, abstract = {We present a numerical and experimental design study for reducing conducted common mode noise for frequencies below 10MHz generated in switching cells comprising sub-nH commutation loops. Compared to conventional methods of adding external gate resistors our approach does not degrade efficiency. A parallel plate loop design (characterized by a minimum loop inductance and small board area usage) is found suboptimal in terms of conducted EMI compared to a micro-strip line loop geometry. The net ground impedance rather than the net ground inductance is found to mainly contribute to the observed EMI noise.}, language = {en} } @article{DechantSeligerKennel2019, author = {Dechant, Eduard and Seliger, Norbert and Kennel, Ralph}, title = {Power cycling and temperature endurance test of a GaN switching cell with substrate integrated chips}, series = {Microelectronics Reliability}, volume = {100-101}, journal = {Microelectronics Reliability}, pages = {113372}, year = {2019}, abstract = {We present a reliability study of a half-bridge switching cell with substrate integrated 650 V GaN HEMTs. Power Cycling Testing with a ΔTj of 100 K has revealed thermo-mechanically induced failures of contact vias after more than 220 kcycles. The via failure mode of contact opening is confirmed by reverse-bias pulsed IV-measurements to be primarily triggered by a ΔTj imposed thermal gradient and not by a high Tj. The chip electrical characteristics, however, remained unaffected during Power Cycling. Furthermore, a High Temperature Storage test at 125 °C for 5000 h has shown no changes in the electrical performance of substrate integrated GaN HEMTs.}, language = {en} }