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We present a model-based optimization approach for the task allocation problem in embedded multi-core systems. The information therefore is obtained from a system description in AUTOSAR and runtime measurements of the runnables in hardware traces. Based on this an initial software partitioning of runnables to tasks is created. We then use a genetic algorithm to create and evaluate solutions to the task allocation problem. Each solution is hereby evaluated using a discrete event-based simulation, which allows the evaluation with regard to real-time properties, resource consumption and data-communication overhead. The significance of our approach is then shown in a case-study. There, we optimize the task allocation of an embedded system, whose complexity is comparable to that of an actual system, on a multi-core processor. Finally, the results of the optimization are transferred to an ECU Configuration Description to enable further development in compliance with the AUTOSAR methodology.
With the availability of the AUTOSAR standard, model-driven methodologies are becoming established in theautomotive domain. However, the process of creating models ofexisting system components is often difficult and time consuming, especially when legacy code has to be re-used or informationabout the exact timing behavior is needed. In order to tackle thisreverse engineering problem, we present CoreTAna, a novel toolthat derives an AUTOSAR compliant model of a real-time systemfrom a dynamic analysis of its trace recordings. This paper givesan overview of CoreTAna's current features and discusses itsbenefits for reverse engineering.
The process of engineering models of existing real-time system components is often difficult and time consuming, especially when legacy code has to be re-used or information about the exact timing behaviour is needed. In order to tackle this reverse engineering problem, we have developed the tool CoreTAna. CoreTAna derives an AUTOSAR compliant model of a real-time system by conducting dynamic analysis using trace recordings.
Motivated by the challenge of assessing the quality of reverse engineered models of real-time software, we present a novel mathematical measure for comparing trace recordings from embedded real-time systems regarding their temporal behaviour. We also introduce a benchmark framework based on this measure, for evaluating reverse engineering tools such as CoreTAna. This considers common system architectures and also includes randomly generated systems and three systems of industrial automotive projects. Finally, an industrial case study demonstrates other use cases of our measure, such as impact analysis.
Safe and reliable multi-core technology becomes more and more important in the field of embedded systems. Today’s and future embedded systems require increasing performance while being more energy efficient. Moreover, the functional safety for these embedded systems has to be improved or developed completely new. In this chapter, we first address the challenges of embedded multi-core real-time systems. To raise the resilience of such systems we use the deadlock-free synchronization model of Block et al. (A flexible real-time locking protocol for multiprocessors. 2012 IEEE international conference on embedded and real-time computing systems and applications, vol 0, pp 47–56, 2007). The metric mean Normalized Blocking Time (mNBT) is hereby used to measure the timing effects of the blocking behavior of strongly interacting tasks. In a second step, we present a model-based approach to map the tasks of an embedded real-time system to the cores of a multi-core processor. Moreover, we derive an execution time model from runtime measurements of software functions. This information is then used to perform precise probabilistic simulations of different task-to-core mappings and evaluate them with regard to task response times, inter-task blocking overhead and load distribution. Subsequently, we integrate the probabilistic simulation within an optimization technique to systematically improve the task-to-core mapping. We conclude with a case-study, where we demonstrate the effectiveness of the presented approach by optimizing the task-to-core mapping of a practical automotive powertrain system.
Automatische Multicore-Echtzeitvalidierung – Ein Prozess für modellbasierte Softwareentwicklung
(2015)
The amount of safety-critical embedded systems in automotive development is heavily growing. Ensuring their reliability not only increases the complexity of functions but also requires determinism at design and execution time, which is considerably challenging to fulfill and verify for multi-core processors. The Logical Execution Time (LET) is recently recognized in automotive industry as an approach for ensuring deterministic functional behavior. However, to decrease the manual design effort and time for deploying such complex systems to multi-core platforms and for ensuring their strict timing and safety requirements, automatic solutions are needed. This work presents a solution for allocating tasks to multi-core processors and generating a time-triggered schedule for embedded systems considering safety, timing, and LET semantics. The approach we propose solves both challenges by defining them as a Constraint Satisfaction Problem (CSP). To examine our CSP formulation, we use MiniZinc, which is a solver-independent constraint modeling language that can employ a variety of solvers. In a case study, we explore optimizations of an industrial system that are enabled by scheduling and task allocation design decisions. Further, the performance of the proposed solutions is evaluated based on large set of synthetically generated system models.