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Development trends for computing platforms moved from increasing the frequency of a single processor to increasing the parallelism with multiple cores on the same die. Multiple cores have strong potential to support cost-efficient fault tolerance due to their inherent spatial redundancy. This work makes a step towards software-only fault tolerance in the presence of permanent and transient hardware faults. Our approach utilizes software-based spatial triple modular redundancy and coded processing on a shared memory multi-core controller. We evaluate our approach on an Infineon AURIX TriBoard TC277 and provide experimental evidence for error resistance by fault injection campaigns with an iSystem iC5000 On-chip Analyzer.
Modelling approaches have to satisfy certain criteria in order to sufficiently encompass the characteristics of dependable heterogenous multi- and many-core system architectures. This work-in-progress paper gives an overview of modern modelling approaches and their related research projects, particularly those regarding domain specific architecture description languages, as well as of the specific challenges of dependable systems and heterogenous multi- and many-core designs, i.e. scheduling techniques for real-time requirements and concerns regarding functional safety. Furthermore, an ongoing research effort in order to identify a set of criteria for evaluating the eligibility of modelling approaches for the task of adequately representing these systems and their specific characteristics is presented.
With parallel applications becoming more and more popular even in real-time systems, the demand for safe and easyto- use software libraries and frameworks for parallel and concurrent computations is growing immensely. These frameworks usually provide an implementation for different sets of software patterns. A very well known software pattern for concurrency is the Active Object pattern, that allows various threads to have synchronized access to an object in question. This paper presents the Parallel Active Object pattern, which extends the common Active Object pattern to support the use of objects, whose computations are profoundly enhanced by a parallel execution. Furthermore, a C++ software framework is introduced, which implements the Parallel Active Object pattern and thus provides the possibility of using task or data parallel patterns, for example Map, Reduce and Divide-and-Conquer, on the active object's calculations. The proposed framework is evaluated against two other popular libraries, namely OpenMP and Intel Threading Building Blocks. Through utilization of the C++11 standard and template classes a simple user interface is provided, which abstracts the distribution of workloads among the worker threads. By making use of the C++ Standard Template Library the framework can easily be ported to embedded systems and by extending the pattern through real-time capabilities, which ensure a timely and reliable execution of the method requests, the intention of providing the framework for time critical environments is also targeted in the future.
In fault tolerant systems, applications are replicated and executed to enable error detection and recovery. If one replica application fails, another is able to take its place and provide the correct results. This concept can benefit from parallel execution on separate execution units. The rise of multicore platforms supports the development of parallel software, by providing the adequate hardware. However, this raises challenges regarding the synchronization of the redundant strings of execution. Replica determinism means that given the same input, identical programs provide the same output. To ensure replica determinism, requirements regarding the synchronization can be split in two domains: data and time. This paper examines the state of the art of synchronization techniques for parallel replicated execution in the context of fault tolerant systems. We analyze the requirements regarding synchronization within the time and data domain and compare different concepts of hardware (multicore, multiprocessor and multi-PCB) and software (processes, threads).
In the recent years the development trends for computing platforms moved to multicore systems. Associated with this trend, feature sizes decreased with each new hardware generation and consequently led to a rise of transient and permanent error frequency in memory and CPUs. In this context, researchers presented several approaches which exploit the inherent redundancy of multicore platforms to provide fault tolerance. We present a discussion of fault tolerance approaches based on redundancy at different levels of architecture regarding theirsphereofreplication,performanceaswellaserrordetection and recovery capability.
Today, due to the rapidly evolving technology within the automotive industry, the automation level of cars is continuously increasing. As a consequence, the software code base implementing the automated driving functionality is growing in both, complexity and size. Simultaneously, the semiconductor industry continues with structure and voltage downscaling due to diminishing design margins and stringent power constraints. This trend leads to highly integrated hardware on the one hand, whilst provoking an increase in sensitivity against external causes for hardware faults, e.g., radiation effects or electromagnetic interference. Among the available dependability assessment techniques, fault injection (FI) is widely adopted and ISO 26262 strongly recommends applying it to validate, that functional and technical safety mechanisms are implemented correctly and effectively. We present PyFI (Python backend for Fault Injection), a fault injection backend for the Infineon Aurix TriCore which utilizes an iSystem On-chip Analyzer to inject faults into the application data or instructions that are visible at the assembly level. PyFI allows the injection of bit flips and stuck-at faults in memory and register cells of the hardware which trigger our error symptoms on application level. Furthermore, it implements fault collapsing algorithms to reduce the number of faults and the duration for single experiments by gathering statistics about the static and dynamic application execution.
The trend towards multi-core systems becomes increasinglyomnipresentandhasalreadyreachedhardreal-time systems. In the recent years more and more researchers tackle the problem of scheduling parallel tasks with real-time constraints. We present a discussion of these recent approaches to hard real-time scheduling tasks consisting of multiple threads. We identify categories in scheduling mechanisms and task systems and discuss their features, as well as the research already achieved in their ???elds. In the domain of task models we identi???ed the gang constrained task model, the order constrained task model and the unconstrained task model. These task models differ regardingtheamountandtypeofthreadexecutionconstraints, which can be expressed using the model. Regarding scheduling algorithms, we identi???ed transformation based and nontransformation based scheduling schemes. The former rely on off-line task transformation, whereas the latter doesn???t require any prior information about task structures. The presented classi???cations show, that applied scheduling algorithms mostly are not restricted to certain task models, but that they are applied quite independently.
New computing-intensive applications such as assisted or highly automated driving are rapidly expanding the domain of safety-critical embedded systems, driven by the vision of the driverless car. This development makes it necessary to use high performance multi-core systems which are commercially available and provide more parallelism in terms of redundant execution units, however, at the cost of being less reliable. With the continuous down-scaling of semiconductor technology, computing hardware exhibits an increasing vulnerability against random hardware faults. Since these high-performance controller provide less or no hardware redundancy to ensure a safe execution of the application, software-only fault tolerance approaches are under current investigation. Our Scalable Software Support for Dependable Embedded Systems (S3DES) approach achieves fault tolerance by utilizing software-based triple modular redundancy for computational and optimized arithmetic encoded voter processes to ensure fault detection and error handling on application level. In S3DES voters are replicated to allow the compensation of voting failures. However, new challenges with regard to error propagation and multiple voting result outputs are introduced by this extension. We describe how mutual voter monitoring and threshold value checks could be used to establish a hierarchy among the replicated voters without re-introducing a reliability bottleneck in the sense of a single point of failure and resolve the aforementioned challenges.
Among the available dependability assessment techniques, fault injection (FI) is widely adopted and strongly recommended by safety standards for the validation that functional and technical safety mechanisms are implemented correctly and effectively. The main challenge in fault injection assessments is the increasing complexity of system-on-chips as well as the increasing size of memory, which leads to enormous efforts to test every possible fault introduced to the system. Therefore, a number of publicly available fault injection frameworks utilize fault space pruning techniques to reduce the overall fault space and consequently the overall experiment duration. Most of the fault space pruning techniques mainly discuss the reduction of the number of data errors which have to be injected into registers and memory locations. However, control flow errors represent a further domain of possible errors on the application level. Usually for the evaluation of effectiveness of fault tolerance mechanisms against data errors, a single fault assumption at microarchitectural level (e.g. bit-flips) is assumed. In most cases, this assumption is equivalently applied to the program counter to investigate possible control flow errors. Due to this approach, the error space is consciously or unconsciously reduced to the possible erroneous jump targets that can be reached by a specific set of bit-flips in the program counter at a specified time during the program execution. This approach is considered valid regarding the corresponding fault assumption, but leads to negative effects on the significance of the injection and the resulting effectiveness of the tested fault tolerance mechanism. In this paper, we discuss different strategies for the analysis and injection of control flow errors and the resulting differences by considering the single fault assumption at microarchitectural and application level.