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Learning centered teaching becomes an important factor in a global perspective of learning software engineering. The Just-in-Time Teaching approach is used in a Chinese-German empirical case study. In a one year terminated project we will analyze the performance of our students in an active learning scenario with Just-in-Time Teaching and Peer Instruction. We will contribute an inter-cultural comparison of achieved competencies by student’s self-assessment and teacher’s observation.
Professional software development is a complex task with many inputs and a complex output. In order to handle complex topics as software or complex engineering projects, structured processes as the V-model or iterative development processes exist. Similarly, the development of a software engineering lecture is a task with many inputs, and a complex output. A structured and methodological approach to the development of a lecture is presented, which applies the same principles as used in the development of software.
Safety has the highest priority because it helps contribute to customer confidence and thereby ensures further growth of the new markets, like electromobility. Therefore in series production redundant hardware concepts like dual core microcontrollers running in lock-step-mode are used to reach for example ASIL D safety requirements given from the ISO 26262. Coded processing is capable of reducing redundancy in hardware by adding diverse redundancy in software, e.g. by specific coding of data and instructions. A system with two coded processing channels is considered. Both channels are active. When one channel fails, the service can be continued with the other channel. It is imaginable that the two channels with implemented coded processing are running with time redundancy on a single core or on a multi core system where for example different ASIL levels are partitioned on different cores. In this paper a redundancy concept based on coded processing will be taken into account. The improvement of the Mean Time To Failure by safeguarding the system with coded processing will be computed for fail-safe as well as for fail-operational systems. The use of the coded processing approach in safeguarding failsafe systems is proved.
The safety of electric vehicles has the highest priority because it helps contribute to customer confidence and thereby ensures further growth of the electromobility market. Therefore in series production redundant hardware concepts like dual core microcontrollers running in lock-step-mode are used to reach ASIL D safety requirements given from the ISO 26262. Coded processing is capable of reducing redundancy in hardware by adding diverse redundancy in software, e.g. by specific coding of data and instructions. A system with two coded processing channels is considered. One channel is active and one is in cold standby. When the active channel fails, the service is switched from the active channel to the standby channel. It is imaginable that the two channels with implemented coded processing are running with time redundancy on a single core or on a multi core system where for example different ASIL levels are partitioned on different cores. In this paper a redundant concept based on coded processing and software rejuvenation will be taken into account.
Capability of single hardware channel for automotive safety applications according to ISO 26262
(2012)
Safety of embedded systems has the highest priority because it helps contribute to customer confidence and thereby ensures growth of the new markets, like electromobility. In series production fail-safe systems as well as fault-tolerant systems are realized with redundant hardware concepts like dual core microcontrollers running in lock-step-mode to reach highest safety requirements given by standards, like ISO 26262 or IEC 61508. In contrast to the hardware redundancy approach, there are also approaches available with information-, time-and/or software-redundancy since several years. One of them is known as coded processing or AN-codes. Coded processing is capable of reducing redundancy in hardware by adding diverse redundancy in software. But the breakthrough of coded processing never took place. One reason for this seem to be the myths which are widely propagated on this subject and the hereby associated uncertainties. In this paper some myths are busted, like the usage of prime numbers as transformation factor A, the myth that greater transformation factors are better or the myth about the residual error probability defined as 1/A. Some of them have been propagated since 1989. The aim of this paper is to provide more clarity and understanding for this technique, perhaps to pave the way for further functional safety concepts based on coded processing approaches.
Mut zu Fehlern, um die Qualität zu steigern – Fault-Injection zur Steigerung der Zuverlässigkeit
(2013)
Wie kann die funktionale Sicherheit in Fahrzeugen zukunftssicher und effektiv gewährleistet werden? Und wie kann dies speziell in elektrifizierten Antrieben gelingen? Mit dieser Aufgabenstellung haben sich AVL in Kooperation mit dem LaS³ und der Universität der Bundeswehr München in einem Forschungsprojekt beschäftigt. Die Antwort lautet: Die automatischen Speichertests in Zusammenspiel mit der Programmfluss-Überwachung und redundanter Hardware können besonders effektiv durch die „Codierte Verarbeitung“ ersetzt werden. Denn hier wird die Diversität in Software erhöht, um die aufwendigere und kostspielige Redundanz von Hardware zu reduzieren.
Diagnostic protocols in automotive systems can offer a huge attack surface with devastating impacts if vulnerabilities are present. This paper shows the application of active automata learning techniques for reverse engineering system state machines of automotive systems. The developed black-box testing strategy is based on diagnostic protocol communication. Through this approach, it is possible to automatically investigate a highly increased attack surface. Based on a new metric, introduced in this paper, we are able to rate the possible attack surface of an entire vehicle or a single Electronic Control Unit (ECU). A novel attack surface metric allows comparisons of different ECUs from different Original Equipment Manufacturers (OEMs), even between different diagnostic protocols. Additionally, we demonstrate the analysis capabilities of our graph-based model to evaluate an ECUs possible attack surface over a lifetime.
Forschungsbericht 2013
(2014)
Forschungsbericht 2017
(2017)
Aufgrund der immer weiter anwachsenden Vernetzung der Stromnetze wird die Kommunikation zwischen der Leitstelle des Energieversorgers und den Infrastrukturkomponenten innerhalb eines Umspannwerks immer bedeutsamer. Dabei werden sowohl Steuerbefehle als auch Daten für Überwachungsfunktionen übertragen. In den aktuellen Netzwerkarchitekturen findet diese Kommunikation ohne eine kryptografische Absicherung statt, was einen Angriffspunkt für gezielte Attacken und damit eine potenzielle Gefährdung der Energieversorgung darstellt. Um solchen Angriffen in Zukunft entgegenzuwirken, wird das ES³M-Sicherheitsmodul entwickelt. Dieses soll in das Netzwerk zwischen den beiden Kommunikationspartnern eingesetzt werden und so den Datenverkehr absichern. Mithilfe einer Bedrohungsanalyse wurden Anforderungen abgeleitet, die neben kryptografischen Maßnahmen auch Themen wie funktionale Sicherheit und Langlebigkeit umfassen. Um diese zu erfüllen, wurde eine spezielle Systemarchitektur auf Basis einer Aufgabenteilung entworfen. Diese Architektur und korrespondierende Designentscheidungen werden präsentiert.
In the field of software engineering, graph-based models are used for a variety of applications. Usually, the layout of those graphs is determined at the discretion of the user. This article empirically investigates whether different layouts affect the comprehensibility or popularity of a graph and whether one can predict the perception of certain aspects in the graph using basic graphical laws from psychology (i.e., Gestalt principles). Data on three distinct layouts of one causal graph is collected from 29 subjects using eye tracking and a print questionnaire. The evaluation of the collected data suggests that the layout of a graph does matter and that the Gestalt principles are a valuable tool for assessing partial aspects of a layout.
Development trends for computing platforms moved from increasing the frequency of a single processor to increasing the parallelism with multiple cores on the same die. Multiple cores have strong potential to support cost-efficient fault tolerance due to their inherent spatial redundancy. This work makes a step towards software-only fault tolerance in the presence of permanent and transient hardware faults. Our approach utilizes software-based spatial triple modular redundancy and coded processing on a shared memory multi-core controller. We evaluate our approach on an Infineon AURIX TriBoard TC277 and provide experimental evidence for error resistance by fault injection campaigns with an iSystem iC5000 On-chip Analyzer.
The requirements for safety-related software systems increases rapidly. To detect arbitrary hardware faults, there are applicable coding mechanism, that add redundancy to the software. In this way it is possible to replace conventional multi-channel hardware and so reduce costs. Arithmetic codes are one possibility of coded processing and are used in this approach. A further approach to increase fault tolerance is the multiple execution of certain critical parts of software. This kind of time redundancy is easily realized by the parallel processing in an operating system. Faults in the program flow can be monitored. No special compilers, that insert additional generated code into the existing program, are required. The usage of multi-core processors would further increase the performance of such multi-channel software systems. In this paper we present the approach of program flow monitoring combined with coded processing, which is encapsulated in a library of coded data types. The program flow monitoring is indirectly realized by means of an operating system.
The Logical Execution Time (LET) has recently been integrated in multi-core automotive systems to ensure timing and dataflow determinism. Although buffering mechanisms are introduced to incorporate LET semantics, they do not guarantee that tasks are executed within their LET frames. In fact, LET and buffering semantics are violated if scheduling is not designed to execute all tasks within their LET frames and in a specific order. In this paper, we describe a scheduling synthesis technique for Fixed-Priority Scheduling (FPS) to achieve resource-efficient execution of LET systems. The proposed approach considers LET semantics, scheduling overheads, and delays caused by operating system operations and provides the possibility to optimize the schedule with respect to aspects like scheduling overheads. Our performance and feasibility evaluation shows that the proposed algorithm provides results in a reasonable amount of time for models of complex industrial applications. Thus, the integration of the proposed algorithm into an automated process is of high benefit to accelerate the development of vehicle applications.