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A family of CMOS low- to high-voltage output interface circuits based on a standard, unmodified low-voltage CMOS technology is described. Using only thin-oxide high-voltage (HV) devices with reduced V/sub GS/ (gate-to-source voltage) swing, it makes use of level-shift techniques to meet the constraints on the gate control signals. These static circuits permit the full output voltage swing of V/sub DDH/, while keeping the V/sub GS/ swing of the output devices within the safety limits, including during HV supply transients. Using a standard 2- mu m n-well CMOS technology, reliable, reproducible V/sub DS/ breakdown voltages as high as 120 V and 80 V have been obtained for HV-nMOS and HV-pMOS devices, respectively.< >
Design and Optimization of High-Voltage CMOS Devices Compatible wih a Standard 5V CMOS Technology
(1993)
High-voltage n- and p-MOSFETs fully compatible with a standard 5 V CMOS technology have been designed, optimized, and fabricated. No process changes are required. By modifying the logical equations generating one of the physical masks from the design masks, a p-type buffer region for the high-voltage p-MOS was easily implemented. This modification does not affect the low-voltage part of the circuits. These high-voltage devices have been used successfully as output drivers in semicustom arrays, and as building blocks for custom low- to high-voltage output interfaces. Aspects of reliability, device protection, and circuit design techniques are addressed.