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The Logical Execution Time (LET) has recently been integrated in multi-core automotive systems to ensure timing and dataflow determinism. Although buffering mechanisms are introduced to incorporate LET semantics, they do not guarantee that tasks are executed within their LET frames. In fact, LET and buffering semantics are violated if scheduling is not designed to execute all tasks within their LET frames and in a specific order. In this paper, we describe a scheduling synthesis technique for Fixed-Priority Scheduling (FPS) to achieve resource-efficient execution of LET systems. The proposed approach considers LET semantics, scheduling overheads, and delays caused by operating system operations and provides the possibility to optimize the schedule with respect to aspects like scheduling overheads. Our performance and feasibility evaluation shows that the proposed algorithm provides results in a reasonable amount of time for models of complex industrial applications. Thus, the integration of the proposed algorithm into an automated process is of high benefit to accelerate the development of vehicle applications.
We present a model-based optimization approach for the task allocation problem in embedded multi-core systems. The information therefore is obtained from a system description in AUTOSAR and runtime measurements of the runnables in hardware traces. Based on this an initial software partitioning of runnables to tasks is created. We then use a genetic algorithm to create and evaluate solutions to the task allocation problem. Each solution is hereby evaluated using a discrete event-based simulation, which allows the evaluation with regard to real-time properties, resource consumption and data-communication overhead. The significance of our approach is then shown in a case-study. There, we optimize the task allocation of an embedded system, whose complexity is comparable to that of an actual system, on a multi-core processor. Finally, the results of the optimization are transferred to an ECU Configuration Description to enable further development in compliance with the AUTOSAR methodology.
Global scheduling algorithms are very promising for application in embedded real-time systems using multi-core controllers. In this paper we want to make a first step forward to apply such scheduling methods on real existing systems. Especially a new resource model is necessary to avoid deadlocks, as this goal can not be achieved by using the standard OSEK Priority Ceiling Protocol when shared global resources are in use. We also introduce the new metric mean Normalized Blocking Time in order to be able to compare locking mechanisms according to the timing effects of their blocking behavior. Finally we give a simulative application example of the new metric by the use of two different kinds of semaphore models and an example task set typical for existing embedded real-time systems in the automotive powertrain environment.
With the availability of the AUTOSAR standard, model-driven methodologies are becoming established in theautomotive domain. However, the process of creating models ofexisting system components is often difficult and time consuming, especially when legacy code has to be re-used or informationabout the exact timing behavior is needed. In order to tackle thisreverse engineering problem, we present CoreTAna, a novel toolthat derives an AUTOSAR compliant model of a real-time systemfrom a dynamic analysis of its trace recordings. This paper givesan overview of CoreTAna's current features and discusses itsbenefits for reverse engineering.
The amount of safety-critical embedded systems in automotive development is heavily growing. Ensuring their reliability not only increases the complexity of functions but also requires determinism at design and execution time, which is considerably challenging to fulfill and verify for multi-core processors. The Logical Execution Time (LET) is recently recognized in automotive industry as an approach for ensuring deterministic functional behavior. However, to decrease the manual design effort and time for deploying such complex systems to multi-core platforms and for ensuring their strict timing and safety requirements, automatic solutions are needed. This work presents a solution for allocating tasks to multi-core processors and generating a time-triggered schedule for embedded systems considering safety, timing, and LET semantics. The approach we propose solves both challenges by defining them as a Constraint Satisfaction Problem (CSP). To examine our CSP formulation, we use MiniZinc, which is a solver-independent constraint modeling language that can employ a variety of solvers. In a case study, we explore optimizations of an industrial system that are enabled by scheduling and task allocation design decisions. Further, the performance of the proposed solutions is evaluated based on large set of synthetically generated system models.
Safe and reliable multi-core technology becomes more and more important in the field of embedded systems. Today’s and future embedded systems require increasing performance while being more energy efficient. Moreover, the functional safety for these embedded systems has to be improved or developed completely new. In this chapter, we first address the challenges of embedded multi-core real-time systems. To raise the resilience of such systems we use the deadlock-free synchronization model of Block et al. (A flexible real-time locking protocol for multiprocessors. 2012 IEEE international conference on embedded and real-time computing systems and applications, vol 0, pp 47–56, 2007). The metric mean Normalized Blocking Time (mNBT) is hereby used to measure the timing effects of the blocking behavior of strongly interacting tasks. In a second step, we present a model-based approach to map the tasks of an embedded real-time system to the cores of a multi-core processor. Moreover, we derive an execution time model from runtime measurements of software functions. This information is then used to perform precise probabilistic simulations of different task-to-core mappings and evaluate them with regard to task response times, inter-task blocking overhead and load distribution. Subsequently, we integrate the probabilistic simulation within an optimization technique to systematically improve the task-to-core mapping. We conclude with a case-study, where we demonstrate the effectiveness of the presented approach by optimizing the task-to-core mapping of a practical automotive powertrain system.