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The mixed-signal event-driven (MixED) simulationalgorithm using standard VHDL is capable of modelinga number of analog and mixed-signal problems in digital circuits, e.g. RCL networks representing pads or wires, charge pumps, dynamic logic, voltage-controlledoscillators, phase-locked loops, etc. Important featuresare single-kernel simulation as well as rapid A/D andD/A interfacing.
This paper demonstrates the simulation of a phase-locked loop (PLL), which is one of the most interesting applications of the MixED method. Many digital designs contain a PLL as only mixed-signal building block. The MixED method allows to simulate such designs with standard VHDL.
This paper describes a very-high-speed integrated-circuit hardware description language (VHDL)-based analog-node model, an associated driver component for the mixed-signal event-driven (MixED) simulation technique, and some primitive device models applied to radio-frequency integrated circuits. With the presented MixED method, analog circuits are modeled as a composition of controlled sources. Unlike other VHDL-based analog simulation methods, these MixED sources compute not only a real number representing an output voltage but also an output impedance. This allows the outputs of several MiXED sources to be connected in order to drive the same node signal n . The voltage of this record-type signal is automatically computed at its element n . u by resolution functions in compliance with Kirchhoff's current law. The data structure of the node signal n , its self-defined resolution functions, and an associated driver component are presented and discussed to meet different simulation requirements, such as speed, versatility, current accuracy, and adaptive time stepping. Several examples demonstrate how to behaviorally model mixed-signal components with this method with an emphasis on the simulation of a heterodyne receiver. Simulation speeds are compared to VHDL-AMS tools.
This communication contemplates political, biological and technical aspects for efficient and profitable irrigation in sustainable agriculture. A standard for irrigation components is proposed. The need for many, and three-dimensionally distributed, soil measurement points is explained, thus enabling the control of humidity in selected layers of earth. Combined wireless and wired data transmission is proposed. Energy harvesting and storage together with mechanical sensor construction are discussed.
A sensor technology for tracking soil-moisture in agricultural fields is presented. A linear measurement method was developed to satisfy the need for cheap sensors with wide range of capacitance change such as factor 30. A combined wired and wireless network transmits data to a server. Various battery aspects are compared with respect to use in agriculture.
A method for solving networks containing generic analog components such as resistors, capacitors and inductors onan event driven time axis using digital VHDL is presented. The components are modeled as complex state machines communicating with their neighbors using INOUT type ports. The method takes advantage of simulation deltas to iterate without simulation-time consumption. A limited range of implicit equations can be solved this way.
Feedback-nach-Feedforward-Transformation zur Verhaltensmodellierung rückgekoppelter Verstärker
(1997)
A method to model high-gain feedback-loop analog amplifiers on an event driven timeaxis is presented. The demonstrator is coded in digital VHDL’93. In the event-driven scheme any node in the network must converge „on its own“ based on the information delivered from its neighbors, as no overall matrix is set up. For this reason signalloops with a loop gain larger than one are typically unstable. This communication presents a numerically stable generic model for high gain amplifiers with a userdefined feedback network. Non-ideal effects like offset or finite gain can be taken into account.
The mixed-signal event-driven (MixED) method developed to simulate small portions of analog circuitry within a digital environment is demonstrated in a mixed signal application. The MixED models using concurrent iteration to account for analog nodes were coded and run in standard VHDL’93. Networks containing linear components such as sources, resistors, capacitors, inductors and operational amplifiers are presented. The possibility to manipulate resistors during runtime is used to simulate switches.
Wireless sensor networks are widely used for environmental monitoring in remote areas. They are mainly composed of wireless sensor nodes, usually powered by batteries with limited capacity, but are expected to communicate in long range and operate for extended time periods. To overcome these limitations, many energy harvesting techniques are proposed to power wireless nodes for prolonged operation, whereas multihop techniques are utilized to extend the communication range. In this paper, a novel floating device with multisource energy harvesting technology that can be used as a wireless sensor node is proposed. The long range communication between wireless sensor nodes and a gateway is established through LoRa technology. In addition to conventional solar panels, an energy harvesting technique based on thermoelectric generators exploiting thermal differences created between water surface and materials exposed to sunlight is proposed. Energy generated from photovoltaic and thermoelectric generators is combined to power the wireless sensor node. This floating device consumes 6.6216 Wh per day when used as a wireless sensor node for the collection and transmission of environmental data. The sensor node can operate on a water surface for at least 9.6 days when it is not exposed to sunlight. During a sunny day, the floating device can harvest 8.375 Wh from solar panels and 0.425 Wh from thermoelectric generation. In other words, the floating device harvests sufficient energy to be self-sustaining during sunny days.
The concept of Industrial Revolution 4.0 (IR4.0) has sparked the urgency of many manufacturers to revisit their manufacturing processes and search for opportunities to further improved their production output. Unfortunately, it is difficult to improve a process with inadequate data. Many of the SMEs in developing countries are still using manufacturing machines from the yesteryears which do not have computational and connectivity capabilities. Therefore, we developed an end-to-end Internet-of-Things (IoT) solution, which reliably tracks the production performance of manufacturing machines. This paper elaborates on the designs and the rationale behind it. As of the writing of this paper, our IoT system has been deployed in real manufacturing environment and has been running for approximately 90 days on a 24/7 basis without data lost.
Quantization and Sampling Effects in Fast Digitally Controlled Switch-Mode DC/DC Buck Converters
(2021)
Software-defined control of DC/DC switch mode power converters features unequaled flexibility compared to analog control. For fast switching converters as recently used for low power applications, digital control may cause steady-state oscillations known as limit cycles. This effect based on a quantized duty cycle is compared to other aberrations such as output ripple voltage, which is inherent to any pulse-width modulator. A distinction is made between DC and AC errors. The latter are divided into synchronous and asynchronous output voltage disturbances. Synchronous AC errors are composed of the switching frequency and its harmonics.
An analytical model for dual-gate-controlled SOI MOSFETs is presented, assuming uniformly doped p-silicon films. It is restricted to electron inversion layers and depletion regions, neglecting hole densities. It allows to account for the spatial description of electronic quantities in the silicon film. Due to the non-linearities of the semiconductor equations the model parameters must be extracted iteratively. Some applications are presented to demonstrate the usefulness of the model.
Distinct electron and hole quasi-Fermi potentials, øf,n and øf,p, are included into a one-dimensional SOI MOSFET model that accounts for finite inversion and depletion layer thicknesses. The inclusion of øf,n, øf,p in the nonlinear analytical model is demonstrated to describe phenomena like kink effect and the multistable-charge-controlled-memory effect (MCCM) in SOI MOSFETs. The calculation of øf,p(t) depends on the device history and generation/recombination rates.
An analytical model for the spatial distribution of potential, electric field and carrier densities is presented, assuming uniform doping density and constant quasi-Fermi potentials in the direction of modeling. Starting from the current relations a differential equation respecting two-dimensional effects is developed and solved approximately by decomposition in three regions with different preconditions: (a) flatband region, (b) constant spacecharge density and (c) strong inversion or accumulation. Inaccuracies arise mainly from violated preconditions at the interfaces between the different regions. Two-dimensional effects are respected in the analytical model of (b) only but they influence region (c) by means of boundary conditions at the interface of (b) and (c).
The investigations of this paper are focused to region (c). This part of our model is identical to the model of Hauser and Littlejohn[1]. They integrated a simplified form of the semiconductor-Poisson equation twice but were restricted to one-dimensional applications and thermal equilibrium. Our derivation allows for large electric fields and current densities perpendicular to the direction of modeling. From analytical considerations confirmed by numerical experiments we suggest preference to the gradual channel condition, with x and y defined according to Fig. 1. This definition allows the potentials to vary significantly with respect to y. We found that this holds for the quasi-Fermi potentials also. Furthermore an empirical model for the maximum width of strong-inversion layers in uniformly doped silicon films is presented in eqn (46).
A family of CMOS low- to high-voltage output interface circuits based on a standard, unmodified low-voltage CMOS technology is described. Using only thin-oxide high-voltage (HV) devices with reduced V/sub GS/ (gate-to-source voltage) swing, it makes use of level-shift techniques to meet the constraints on the gate control signals. These static circuits permit the full output voltage swing of V/sub DDH/, while keeping the V/sub GS/ swing of the output devices within the safety limits, including during HV supply transients. Using a standard 2- mu m n-well CMOS technology, reliable, reproducible V/sub DS/ breakdown voltages as high as 120 V and 80 V have been obtained for HV-nMOS and HV-pMOS devices, respectively.< >
Design and Optimization of High-Voltage CMOS Devices Compatible wih a Standard 5V CMOS Technology
(1993)
High-voltage n- and p-MOSFETs fully compatible with a standard 5 V CMOS technology have been designed, optimized, and fabricated. No process changes are required. By modifying the logical equations generating one of the physical masks from the design masks, a p-type buffer region for the high-voltage p-MOS was easily implemented. This modification does not affect the low-voltage part of the circuits. These high-voltage devices have been used successfully as output drivers in semicustom arrays, and as building blocks for custom low- to high-voltage output interfaces. Aspects of reliability, device protection, and circuit design techniques are addressed.
A one-dimensional analytical model for dual-gate-controlled SOI MOSFETs is presented and applied to a stacked p-channel MOSFET fabricated by epitaxial lateral overgrowth (ELO). The authors found and modeled a nonlinear dependence of front-gate threshold voltage on back-gate voltage if threshold is defined by a constant current instead of a constant silicon-surface potential. It is demonstrated by comparison of subthreshold slopes that surface potentials are not pinned to the onset of strong inversion or accumulation. Accurate one-dimensional modeling is a necessity for device characterization and a precondition for general SOI models for circuit simulation.< >
La présente invention concerne un circuit intermédiaire entre un circuit logique a basse tension et un étage de sortie à haute tension réalisés dans une technologie CMOS standard. L'étage de sortie (20) comporte deux transistors respectivement à canal N et à canal P, réalisés selon une technologie CMOS standard. Le circuit intermédiaire comporte un translateur de niveau de tension (21) couplé entre un circuit logique d'entrée SL et ledit étage de sortie (20). Ce translateur de niveau de tension (21) est réalisé selon une technologie CMOS standard et est constitué d'au moins deux blocs de base identiques formant des miroirs de tension interconnectés de façon croisée. Ce circuit est utilisé pour commander des transducteurs, des écrans plasma et des actionneurs électromécaniques.