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Fabrication and simulation of silicon structures with high aspect ratio for field emission devices
(2014)
To obtain higher field enhancement factors of Si-tip structures, we present an improved fabrication process utilizing reactive-ion etching (RIE) with an inductively coupled plasma (ICP). In our design, a pillar under the tips is realized by a combination of RIE with ICP. With adjusted power settings (≈ 240 W) and step times (<; 5 s), vertical slopes with a low roughness of approximately 10 nm to 20 nm are possible. The remaining silicon is oxidized thermally to sharpen the emitters. A final tip radius of R <; 20 nm is obtained for the tips of the emitters. The pillar height HP can be mainly adjusted by the duration of the ICP-etching step. A total emitter height of H ≈ 6 μm with a pillar height of HP ≈ 5 μm is achieved. Simulations with COMSOL Multiphysics® are applied to calculate the field enhancement factor β. A two-dimensional model is used in rotational symmetry. In addition to the previous model, a pillar with a varying diameter ØP and height HP is added. A conventional emitter (H = 1 μm and R = 20 nm) placed on a pillar of the height HP ≈ 5 μm approximately results in a three times higher β-factor (β≈ 105). By decreasing the diameter ØP a slight increase of the β-factor is observed. However, the aspect ratio of the emitter mainly influences on the β-factor.
The homogeneity of emitters is very important for the performance of field emission (FE) devices. Reactive-ion etching (RIE) and oxidation have significant influences on the geometry of silicon tips. The RIE influences mainly the anisotropy of the emitters. Pressure has a strong impact on the anisotropic factor. Reducing the pressure results in a higher anisotropy, but the etch rate is also lower. A longer time of etching compensates this effect. Furthermore an improvement of homogeneity was observed. The impact of uprating is quite low for the anisotropic factor, but significant for the homogeneity. At low power the height and undercut of the emitters are more constant over the whole wafer. The oxidation itself is very homogeneous and has no observable effect on further variation of the homogeneity. This modified fabrication process allows solving the problem of inhomogeneity of previous field emission arrays.
Precisely aligned arrays of sharp tip structures on top of elongated pillars were realized by using an improved fabrication process including an additional inductively-coupled-plasma reactive-ion etching step. Arrays of n-type and p-type silicon with 271 tips have been fabricated and investigated. Those structures have a total height of 5–6 µm and apex radii less than 20nm. Integral field emission measurements of the arrays yielded low onset-fields in the range of 8–12V=µm and field enhancement factors between 300 and 700. The I-E curves of n-type structures showed the usual Fowler-Nordheim behaviour, whereas p-type structures revealed a significant saturation region due to the limited number of electrons in the conduction band and a further carrier depletion effect caused by the pillar. The maximum integral current in the saturation region was 150 nA at fields above 30V=µm. An excellent stability of the emission current of less than ± 2% fluctuation was observed in the saturation region. For n-type Si a maximum integral current of 10 µA at 24V=µm and an average current stability with a fluctuation of ± 50% were measured.
We report on the simulation and fabrication of nanostructured silicon surfaces for field emission (FE) applications, e.g. ionization sensors and x-ray tubes. For the design and optimization of field-emitting silicon structures, the influence of the geometric parameters like tip height, apex radius, aperture angle and curvature shape on the field enhancement factor was investigated by simulation using finite element method. A universal geometric model which describes the real geometry of our silicon structures sufficiently accurate was taken for modeling a variety of different silicon tip structures as well as ridge structures. While a high dependency of the field enhancement on the aspect ratio and the aperture angle was found, the simulations show that the elliptic curvature affects the field enhancement only marginally. Finally, an improved process for fabrication of such silicon structures on n-type as well as p-type substrate is described, using reactive ion etching with adjustable anisotropy, wet thermal oxidation and wet etching.
The homogeneity of emitters is very important for the performance of field emission (FE) devices. Reactive-ion etching (RIE) and oxidation have significant influences on the geometry of silicon tips. The RIE influences mainly the anisotropy of the emitters. Pressure has a strong impact on the anisotropic factor. Reducing the pressure results in a higher anisotropy, but the etch rate is also lower. A longer time of etching compensates this effect. Furthermore an improvement of homogeneity was observed. The impact of uprating is quite low for the anisotropic factor, but significant for the homogeneity. At low power the height and undercut of the emitters are more constant over the whole wafer. The oxidation itself is very homogeneous and has no observable effect on further variation of the homogeneity. This modified fabrication process allows solving the problem of inhomogeneity of previous field emission arrays.
We report on miniaturized silicon field emitter arrays for the application in compact and energy-saving vacuum-microelectronic devices, e.g. sensors or x-ray tubes. Since standard silicon semiconductor technology has been used for the fabrication, they may be easily integrated with other silicon based circuits and devices on the same chip. The silicon tip geometry and the operating conditions were optimized in order to obtain highly uniform and stable electron field emission from large area cathode arrays. A series of uniform hexagonal tip arrays containing each 547 tips were fabricated and characterized. The electron emission properties of both individual tips as well as of complete emitter arrays were investigated. A saturation level in the voltage-current characteristics was found, which can be explained by the limitation of the supply of electrons due to the p-type silicon wafer material. When operating the arrays in the current saturation regime at an emission current of ~ 1 nA per tip, a highly stable and low noise emission can be observed.