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5V-to-75V CMOS Output Interfaces

  • A family of CMOS low- to high-voltage output interface circuits based on a standard, unmodified low-voltage CMOS technology is described. Using only thin-oxide high-voltage (HV) devices with reduced V/sub GS/ (gate-to-source voltage) swing, it makes use of level-shift techniques to meet the constraints on the gate control signals. These static circuits permit the full output voltage swing of V/sub DDH/, while keeping the V/sub GS/ swing of the output devices within the safety limits, including during HV supply transients. Using a standard 2- mu m n-well CMOS technology, reliable, reproducible V/sub DS/ breakdown voltages as high as 120 V and 80 V have been obtained for HV-nMOS and HV-pMOS devices, respectively.< >

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Metadaten
Author:Michel Declerq, Martin J. W. Schubert, F. Clément
DOI:https://doi.org/10.1109/ISSCC.1993.280014
Parent Title (English):Proceedings of the1993 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 24-26 1993, San Francisco, CA, USA
Document Type:conference proceeding (article)
Language:English
Year of first Publication:1993
Release Date:2021/04/01
First Page:162
Last Page:163
Institutes:Fakultät Elektro- und Informationstechnik
Fakultät Elektro- und Informationstechnik / Labor Elektronik
Publication:Externe Publikationen
research focus:Produktion und Systeme
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