A Multicore Fault Tolerance Approach Based on Coded Processing
- Development trends for computing platforms moved from increasing the frequency of a single processor to increasing the parallelism with multiple cores on the same die. Multiple cores have strong potential to support cost-efficient fault tolerance due to their inherent spatial redundancy. This work makes a step towards software-only fault tolerance in the presence of permanent and transient hardware faults. Our approach utilizes software-based spatial triple modular redundancy and coded processing on a shared memory multi-core controller. We evaluate our approach on an Infineon AURIX TriBoard TC277 and provide experimental evidence for error resistance by fault injection campaigns with an iSystem iC5000 On-chip Analyzer.
Author: | Lukas Osinski, Jürgen MottokORCiDGND |
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URL / DOI: | https://hal.archives-ouvertes.fr/hal-02156233 |
Parent Title (English): | Embedded Real-Time Software and Systems Conference (ERST²), Jan 2018, Toulouse/France |
Document Type: | conference proceeding (article) |
Language: | English |
Year of first Publication: | 2018 |
Release Date: | 2021/03/11 |
Institutes: | Fakultät Elektro- und Informationstechnik |
Fakultät Elektro- und Informationstechnik / Laboratory for Safe and Secure Systems (LAS3) | |
research focus: | Digitalisierung |
OpenAccess Publikationsweg: | Diamond Open Access - OA-Veröffentlichung ohne Publikationskosten (Sponsoring) |
Licence (German): | Keine Lizenz - Es gilt das deutsche Urheberrecht: § 53 UrhG |