TY - CHAP A1 - Renner, Sebastian A1 - Pozzobon, Enrico A1 - Mottok, Jürgen ED - Meng, Weizhi T1 - A Hardware in the Loop Benchmark Suite to Evaluate NIST LWC Ciphers on Microcontrollers T2 - Information and Communications Security: 22nd International Conference, ICICS 2020, Copenhagen, Denmark, August 24-26, 2020, Proceedings N2 - The National Institute of Standards and Technology (NIST) started the standardization process for lightweight cryptography algorithms in 2018. By the end of the first round, 32 submissions have been selected as 2nd round candidates. NIST allowed designers of 2nd round submissions to provide small updates on both their specifications and implementation packages. In this work, we introduce a benchmarking framework for evaluating the performance of NIST Lightweight Cryptography (LWC) candidates on embedded platforms. We show the features and application of the framework and explain its design rationale. Moreover, we provide information on how we aim to present up-to-date performance figures throughout the NIST LWC competition. In this paper, we present an excerpt of our software benchmarking results regarding speed and memory requirements of selected ciphers. All up-to-date results, including benchmarking different test cases for multiple variants of each 2nd round algorithm on five different microcontrollers, are periodically published to a public website. While initially only the reference implementations were available, the ability of automatically testing the performance of the candidate algorithms on multiple platforms becomes especially relevant as more optimized implementations are developed. Finally, we show how the framework can be extended in different directions: support for more target platforms can be easily added, different kinds of algorithms can be tested, and other test metrics can be acquired. The focus of this paper should rather lay on the framework design and testing methodology than on the current results, especially for reference code. KW - Lightweight cryptography KW - Benchmarking KW - Embedded systems KW - RISC-V Y1 - 2020 U6 - https://doi.org/10.1007/978-3-030-61078-4_28 SP - 495 EP - 509 PB - Springer CY - Cham ER - TY - CHAP A1 - Reuter, Rebecca A1 - Stark, Theresa A1 - Sedelmaier, Yvonne A1 - Landes, Dieter A1 - Mottok, Jürgen A1 - Wolff, Christian T1 - Insights in Students’ Problems during UML Modeling T2 - 2020 IEEE Global Engineering Education Conference (EDUCON): Proceedings N2 - UML (Unified Modeling Language) is the current de facto as well as de jure standard (ISO/IEC 19505:2012) notation to visualize models in software development. UML provides essential guidelines and rules to visualize and understand complex software systems. This is the reason why it has become part of curricula for software engineering courses at many universities worldwide. It is well known, however, that UML is hard to grasp for novices, mainly due to its complexity. In order to tackle the problem of teaching UML to novice students appropriately, it is inevitable to understand their needs and problems much better than we do now. This paper presents empirical insights into students' problems when developing common UML diagrams. Identified problems are generalized, giving rise to a problem catalogue that is derived from our empirical findings, thus establishing a basis for addressing these problems through focused learning arrangements. KW - UML KW - UML problems KW - software engineering KW - higher education KW - visual notation Y1 - 2020 U6 - https://doi.org/10.1109/EDUCON45650.2020.9125110 SP - 592 EP - 600 ER - TY - CHAP A1 - Gruber, Hans A1 - Wolff, Christian A1 - Mottok, Jürgen A1 - Bazo, Alexander A1 - Hauser, Florian A1 - Schreistetter, Stefan T1 - Tutorial on Software Engineering Education in Co-Located Multi-User Eye-Tracking-Environments T2 - Proceedings of the 32nd IEEE Conference on Software Engineering Education and Training: Munich, November 2020 N2 - We briefly describe a tutorial on the application of Eye-Tracking technology for Software Engineering Education. We will showcase our setup of a large-scale Eye-Tracking-Classroom and its usage for real-time improvement of traditional learning scenarios in Software Engineering Education. We will focus on the integration of gaze data into modern integrated development environments (IDEs) and demonstrate a complete workflow for its usage in co-located multi-user Eye-Tracking-Environments. KW - eye-tracking KW - software engineering education KW - multi-user eye tracking KW - real-time learning scenarios Y1 - 2020 U6 - https://doi.org/10.1109/CSEET49119.2020.9206170 ER - TY - CHAP A1 - Inderwies, Tom A1 - Mottok, Jürgen T1 - Secure Software Update of a Secure Module in the Power Grid T2 - Proceedings of the Regensburg Applied Research Conference 2020 (RARC 2020), July 31st Y1 - 2020 UR - https://doi.org/10.35096/othr/pub-641 SP - 25 EP - 31 ER - TY - CHAP A1 - Hauser, Florian A1 - Schreistetter, Stefan A1 - Reuter, Rebecca A1 - Mottok, Jürgen A1 - Gruber, Hans A1 - Holmqvist, Kenneth A1 - Schorr, Nick T1 - Code reviews in C++: Preliminary results from an eye tracking study T2 - ETRA '20 Short Papers: ACM Symposium on Eye Tracking Research and ApplicationsJune 2020 N2 - Code reviews are an essential part of quality assurance in modern software projects. But despite their great importance, they are still carried out in a way that relies on human skills and decisions. During the last decade, there have been several publications on code reviews using eye tracking as a method, but only a few studies have focused on the performance differences between experts and novices. To get a deeper understanding of these differences, the following experiment was developed: This study surveys expertise-related differences in experts’, advanced programmers’, and novices’ eye movements during the review of eight short C++ code examples, including correct and erroneous codes. A sample of 35 participants (21 novices, 14 advanced and expert programmers) were recruited. A Tobii Spectrum 600 was used for the data collection. Measures included participants’ eye movements during the code review, demographic background data, and cued retrospective verbal comments on replays of their own eye movement recordings. Preliminary results give proof for experience-related differences between participants. Advanced and expert programmers performed significantly better in case of error detection and the eye tracking data implies a more efficient reviewing strategy. Y1 - 2020 SN - ISBN 9781450371346 U6 - https://doi.org/10.1145/3379156.3391980 SP - 1 EP - 5 ER - TY - CHAP A1 - Hauser, Florian A1 - Stark, Theresa A1 - Mottok, Jürgen A1 - Gruber, Hans A1 - Reuter, Rebecca T1 - Deliberate Practice in Programming: How is it carried out by programmers? T2 - ECSEE '20: Proceedings of the 4th European Conference on Software Engineering Education, Seeon, Germany, June 2020 N2 - This work in progress study examines through which activities programmers perform deliberate practice to improve their own skills in coding and programming. For this reason, a qualitative questionnaire was developed and conducted with a sample of 22 participants. The results indicate that programmers perform formal and informal forms of training and learning. Typically, a classical programming training in the context of a university course or for work-related reasons is a first step in the acquisition of expertise. Building on these basic skills, non-formal and informal learning activities are carried out by the learners. Especially the social interaction and the collaborative work with other programmers is of great importance in this context. The activities mentioned by the test persons fulfil the characteristics of deliberate practice and will be examined more closely in a further study. Y1 - 2020 SN - ISBN 9781450377522 U6 - https://doi.org/10.1145/3396802.3396815 SP - 42 EP - 46 ER - TY - CHAP A1 - Schmid, Michael A1 - Fritz, Florian A1 - Mottok, Jürgen T1 - Parallel Programming in Real-Time Systems T2 - Architecture of computing systems - ARCS 2019, 32nd international conference, Copenhagen, Denmark, May 20-21, 2019, proceedings N2 - The enormous amounts of data modern real-time systems have to process lead to expensive, long-lasting calculations. In order to manage those computations in a timely manner, parallel task models have gained a lot of popularity lately. However, parallel programming can be very cumbersome and verbose. Other computationally intensive sectors have dealt with parallel computing for decades and have accumulated their experience in the development of parallel frameworks. Examples of well known parallel runtime systems are OpenMP, Intel Threading Building Blocks (TBB) and Microsoft Parallel Pattern Library (PPL). These runtime systems allow developers to enhance parallelism in their applications in a straightforward fashion. However, those parallel frameworks and the patternbased interfaces they provide might not be easily applicable in real-time systems. In this paper, we investigate the use of parallel programming frameworks in time-critical systems. On that account, we discuss considerations for the design of real-time applications that make use of such parallel runtime systems. Furthermore, we evaluate three library-based frameworks from different computing sectors, namely Intel Threading Building Blocks, Embedded Multicore Building Blocks (EMBB) and High Performance ParalleX (HPX), by conducting benchmarks of various parallel algorithms on an embedded multicore architecture. Y1 - 2019 UR - https://ieeexplore.ieee.org/abstract/document/8836206 PB - VDE-Verlag CY - Berlin ER - TY - CHAP A1 - Mottok, Jürgen A1 - Schiller, Frank A1 - Völkl, Thomas A1 - Zeitler, Thomas T1 - A concept for a safe realization of a state machine in embedded automotive applications T2 - Computer safety, reliability, and security, 26th International Conference, SAFECOMP 2007, Nuremberg, Germany, September 18-21, 2007; proceedings N2 - Currently, both fail safe and fail operational architectures are based on hardware redundancy in automotive embedded systems. In contrast to this approach, safety is either a result of diverse software channels or of one channel of specifically coded software within the framework of Safely Embedded Software. Product costs are reduced and flexibility is increased. The overall concept is inspired by the well-known Vital Coded Processor approach. Since Mealy state machines are frequently used in embedded automotive systems, application software with a general Mealy state machine is realized differently with Safely Embedded Software starting from the high level programming language C with corresponding measurements. KW - Safely KW - Embedded Software KW - Safe State Machine KW - Diverse Instructions KW - Safety Code Weaving KW - Safety Supervisor Y1 - 2007 U6 - https://doi.org/10.1007/978-3-540-75101-4_2 SP - 283 EP - 288 ER - TY - JOUR A1 - Hummel, M. A1 - Mottok, Jürgen A1 - Egen, R. A1 - Schiller, Frank A1 - Mattes, T. A1 - Blum, M. A1 - Druckstein, F. T1 - Generische Safety-Architektur für Kfz-Software JF - Spektrum, das Magazin der Hochschule Regensburg Y1 - 2007 CY - Regensburg ER - TY - JOUR A1 - Schiller, Frank A1 - Mottok, Jürgen A1 - Blum, M. A1 - Duckstein, F. A1 - Egen, R. A1 - Hummel, M. A1 - Mattes, T. T1 - Generische Safety-Architektur für KFZ-Software JF - Hanser automotive Y1 - 2006 SP - 52 EP - 54 ER - TY - CHAP A1 - Deubzer, Michael A1 - Mottok, Jürgen A1 - Flug, Christian A1 - Zeitler, Thomas T1 - Profiling Performance Analyse von Embedded Real-Time System Architekturen T2 - Embedded Software Engineering Kongress, Tagungsband ; 8. bis 10. Dezember 2008, Sindelfingen Y1 - 2008 SP - 155 EP - 167 ER - TY - JOUR A1 - Federrath, H. A1 - Mottok, Jürgen A1 - Plößl, K. A1 - Völkl, Thomas T1 - Automotive safety and security JF - Jahresrückblick 2007 des Bayerischen IT-Sicherheitsclusters Y1 - 2007 ER - TY - CHAP A1 - Schmidt, Peter A1 - Mottok, Jürgen T1 - "Werkstattbericht" Bioagile Softwareentwicklung T2 - Embedded Software Engineering Kongress, Tagungsband ; 8. bis 10. Dezember 2008, Sindelfingen Y1 - 2008 SP - 455 EP - 460 ER - TY - CHAP A1 - Mottok, Jürgen A1 - Schiller, Frank T1 - MISRA C++:2008 and safely embedded software – a safety framework for C++ T2 - Proceedings of the Automotive Safety & Security Conference Y1 - 2008 UR - http://docplayer.org/53952332-Misra-c-2008-safely-embedded-software-ses.html ER - TY - CHAP A1 - Schirdewahn, B. A1 - Mottok, Jürgen T1 - Implementierungslösungen für die Eigenentwicklung eines deterministischen, nicht preemptiven Echtzeit Betriebssystems zur Verwaltung eingebetteter Applikationen T2 - Embedded Software Engineering Kongress, Tagungsband ; 8. bis 10. Dezember 2008, Sindelfingen Y1 - 2008 SP - 141 EP - 147 ER - TY - JOUR A1 - Mottok, Jürgen T1 - Aktuelle Forschungsergebnisse aus dem "Laboratory for Safe and Secure Systems"(LaS3) JF - Jahresrückblick 2008 des Bayerischen IT-Sicherheitsclusters Y1 - 2008 SP - 13 EP - 15 ER - TY - CHAP A1 - Mottok, Jürgen A1 - Schiller, Frank T1 - Safely embedded software and MISRA C++: 2008 – a safety framework for c++ T2 - Proceedings of the SAFETY@SIEMENS Conference Y1 - 2008 ER - TY - CHAP A1 - Mottok, Jürgen T1 - Safely embedded software- a safety framework for c++ T2 - Proceedings of the 1st Embedded Software Engineering Conference, 8. bis 10. Dezember 2008, Sindelfingen Y1 - 2008 SP - 444 EP - 449 ER - TY - CHAP A1 - Deubzer, Michael A1 - Margull, Ulrich A1 - Mottok, Jürgen A1 - Niemetz, Michael A1 - Wirrer, Gerhard T1 - Partitionierungs-Scheduling von Automotive Restricted Tasksystemen auf Multiprozessorplattformen T2 - Proceedings of the 2nd Embedded Software Engineering Congress, 8. bis 10. Dezember 2009, Sindelfingen Y1 - 2009 SP - 536 EP - 542 ER - TY - CHAP A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Modifikation des Taskzustandsmodells des LLREF-Schedulers auf einem Dual-Core-Prozessor T2 - Proceedings of the 2nd Embedded Software Engineering Congress, 8. bis 10. Dezember 2009, Sindelfingen Y1 - 2009 SP - 628 EP - 636 ER - TY - CHAP A1 - Mottok, Jürgen A1 - Hagel, Georg A1 - Utesch, Matthias A1 - Waldherr, Franz T1 - Konstruktivistische Didaktik - ein Rezept für eine bessere Software Engineering Ausbildung? T2 - Proceedings of the 2nd Embedded Software Engineering Congress, 8. bis 10. Dezember 2009, Sindelfingen Y1 - 2009 SP - 601 EP - 610 ER - TY - CHAP A1 - Schmidt, Peter A1 - Mottok, Jürgen T1 - Memorandum der Bioagile Software- und Systementwicklung T2 - Proceedings of the 2nd Embedded Software Engineering Congress, 8. bis 10. Dezember 2009, Sindelfingen Y1 - 2009 SP - 487 EP - 497 ER - TY - CHAP A1 - Bärwald, Andreas A1 - Hauff, Harald A1 - Mottok, Jürgen T1 - Qualification and certification of development tools for safety-critical applications T2 - Proceedings of Dependability@SIEMENS Conference N2 - This paper presents an overview on qualification and certification of tools used in the phases of the safety lifecycle for safety-critical applications, either for development or for verification and validation. Software development tools are widely used in the development of safety-critical software systems. More verification and validation procedures will be automated by software tools to reduce time consuming manual testing. The impact of software tools on functional safety is discussed. Based on normative regulations like IEC 61508 and ISO DIS 26262 different approaches for tool qualification and certification are presented. Y1 - 2009 ER - TY - JOUR A1 - Hartig, Wolfgang A1 - Habermann, Albert A1 - Mottok, Jürgen T1 - Mehr Qualität durch modellbasiertes Testen JF - Elektronik automotive 3 Y1 - 2009 UR - https://www.elektroniknet.de/automotive/software-tools/mehr-qualitaet-durch-modellbasiertes-testen.1370.html SP - 32 EP - 35 ER - TY - CHAP A1 - Steindl, Michael A1 - Mottok, Jürgen A1 - Meier, Hans A1 - Schiller, Frank A1 - Früchtl, M. T1 - Diskussion des Einsatzes von Safely Embedded Software in FPGA-Architekturen T2 - Proceedings of the 2nd Embedded Software Engineering Congress, 8. bis 10. Dezember 2009, Sindelfingen Y1 - 2009 SP - 655 EP - 661 ER - TY - CHAP A1 - Studt, Reimer A1 - Mottok, Jürgen A1 - Utesch, Matthias A1 - Landes, Dieter T1 - Anwendung der Bloom´schen Taxonomie auf Lehrinhalte des Software-Engineerings T2 - Proceedings of the 2nd Embedded Software Engineering Congress, 8. bis 10. Dezember 2009, Sindelfingen Y1 - 2009 SP - 583 EP - 593 ER - TY - CHAP A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Modifikation des Taskzustandsmodells des LLREF-Schedulers auf einem Dual-Core-Prozess T2 - Proceedings of the 2nd Embedded Software Engineering Congress, 8. bis 10. Dezember 2009, Sindelfingen Y1 - 2009 SP - 628 EP - 636 ER - TY - CHAP A1 - Schorer, Michael A1 - Kuntz, Stefan A1 - Mottok, Jürgen T1 - Beschreibung eines kooperativen Tasksystems mit OSEK-konformen Scheduler durch Petri Netze T2 - Proceedings of the 2nd Embedded Software Engineering Congress, 8. bis 10. Dezember 2009, Sindelfingen Y1 - 2009 SP - 637 EP - 644 ER - TY - CHAP A1 - Stamatescu, G. A1 - Deubzer, Michael A1 - Mottok, Jürgen A1 - Popescu, Dan T1 - Migration overhead in multiprocessor scheduling T2 - Proceedings of the 2nd Embedded Software Engineering Congress, 8. bis 10. Dezember 2009, Sindelfingen Y1 - 2009 SP - 645 EP - 654 ER - TY - JOUR A1 - Hartig, Wolfgang A1 - Habermann, Albert A1 - Mottok, Jürgen T1 - Model-based testing for better quality JF - Vector, Technicle Article Y1 - 2009 ER - TY - JOUR A1 - Mottok, Jürgen T1 - Safely embedded software JF - Embedded Software Engineering Report Y1 - 2009 VL - 53 SP - 10 EP - 11 ER - TY - CHAP A1 - Steindl, Michael A1 - Mottok, Jürgen A1 - Meier, Hans A1 - Schiller, Frank A1 - Früchtl, M. T1 - Safeguarded Processing of Sensor Data T2 - IT-SecurityArea (IT-SA 2009) vom 13.-15. Oktober 2009, Nürnberg N2 - The spectrum of software tasks no longer includes only rare function controlling tasks for sensor actuator chains in reactive embedded systems. However, more and more responsible challenges like safety-critical scenarios are tackled. Therefore sensor data have to be safeguarded by several mechanism. An obvious and widely used approach is the use of two redundant hardware controllers, but this comes along with an additional cost, space and energy factor. Another way to fulfill certain safety properties is to implement a second diverse software channel in a single micro-controller architecture according the Safely Embedded Software (SES) approach. However, a lack of performance occurs by implementing this diverse channel for complex computations e.g. floating-point operations. This paper gives an approach for transferring the SES into a coprocessor and to migrate SES to a flexible and powerful FPGA architecture. KW - Safety embedded software KW - FPGA KW - Diverse instructions KW - Safety code weaving Y1 - 2009 UR - https://hal.archives-ouvertes.fr/hal-02268737 ER - TY - JOUR A1 - Deubzer, Michael A1 - Mottok, Jürgen A1 - Bärwald, Andreas T1 - Dependability-Betrachtung von Multicore-Scheduling JF - HANSER Automotive N2 - Der Embedded Markt stellt sich auf eine neue Herausforderung ein: denUmstieg von Singlecore- auf Multicore-Prozessorsysteme. Dabei soll dieUmsetzung der Norm ISO 26262 die Funktionale Sicherheit der elektri-schen und elektronischen Systeme im Kraftfahrzeug gewährleisten. In diesem Beitrag betrachten die Hochschule Regensburg und die TÜV SüdAutomotive GmbH das Scheduling eines Echtzeitsystems als ein sicher-heitsrelevantes Sub-System. Y1 - 2010 UR - https://res.cloudinary.com/sternwald-systems/raw/upload/v1/hugoprd/ARTIKEL_ATTACH/00207DD4_0669BA3F5B24/4b2124fb030a4d3d5a42a83aaec4bddadebe3077/AM_2010_11_Dependability-Betrachtung-von-Multicore-Scheduling.pdf IS - 11 SP - 24 EP - 27 ER - TY - CHAP A1 - Bierl, Rudolf A1 - Boehm, M. A1 - Fraunhoffer, Judith A1 - Gardeia, Armin A1 - Mottok, Jürgen A1 - Schneider, Ralph A1 - Streubel, J. T1 - “Regensburger Modell zu den P-Seminaren” – Ein Konzept zur Gestaltung der Schnittstelle Gymnasium – Hochschule und zur Praxis einer kooperativen Lehr-Lern-Didaktik für Informationstechnik T2 - 3rd Embedded Software Engineering Congress, 7. bis 9. Dezember, Sindelfingen Y1 - 2010 PB - Vogel Business Media CY - Würzburg ER - TY - CHAP A1 - Hagel, Georg A1 - Mottok, Jürgen A1 - Utesch, Matthias A1 - Landes, Dieter A1 - Studt, Reimer T1 - Software Engineering Lernen für die berufliche Praxis – Erfahrungen mit dem konstruktivistischen Methodenbaukasten T2 - Proceedings of the 3rd Embedded Software Engineering Congress, 7. bis 9. Dezember 2010, Sindelfingen Y1 - 2010 ER - TY - CHAP A1 - Braun, Jürgen A1 - Mottok, Jürgen A1 - Miedl, Christian A1 - Greyer, D. A1 - Minas, Mark T1 - Fail-Safe und Fault-Tolerant Mechanismen T2 - Proceedings of the 3rd Embedded Software Engineering Congress, 7. bis 9. Dezember 2010, Sindelfingen Y1 - 2010 SP - 378 EP - 386 ER - TY - CHAP A1 - Steindl, Michael A1 - Mottok, Jürgen A1 - Meier, Hans A1 - Schiller, Frank A1 - Früchtl, M. T1 - Migration of SES to FPGA Based Architectural Concepts T2 - Proceedings of the Workshop 'Safely embedded software' Y1 - 2009 ER - TY - JOUR A1 - Deubzer, Michael A1 - Mottok, Jürgen T1 - Dependability von Systemen mit dynamischen Multicore-Schedulingalgorithmen JF - safetronic Y1 - 2010 ER - TY - JOUR A1 - Raab, Peter A1 - Mottok, Jürgen A1 - Meier, Hans T1 - OSEK-RTOS für Jedermann (Teil 2) JF - Embedded Software Engineering Report Y1 - 2009 VL - 53 SP - 10 EP - 12 ER - TY - JOUR A1 - Raab, Peter A1 - Mottok, Jürgen A1 - Meier, Hans T1 - OSEK-RTOS für Jedermann (Teil 1) JF - Embedded Software Engineering Report Y1 - 2009 VL - 53 IS - September SP - 14 EP - 15 ER - TY - JOUR A1 - Deubzer, Michael A1 - Mottok, Jürgen A1 - Margull, Ulrich A1 - Niemetz, Michael A1 - Wirrer, Gerhard T1 - Efficient Scheduling of Reliable Automotive Multi-core Systems with PD² by Weakening ERfair Task System Requirements JF - Automotive Safety and Security N2 - Partly Proportionate fair (Partly-Pfair) scheduling, which allows task migration at runtime and assigns each task processing time with regard to its weight, makes it possible to build highly efficient embedded multi-core systems. Due to its non-work-conserving behavior, which might leave the CPU idle even when tasks are ready to execute, tasks finish only shortly before their deadlines are reached. Benefits are lower task jitter, but additional workload, e.g. through interrupts, can lead to deadline violations. In this paper we present a work-conserving extension of Partly-Pfair scheduling, called PERfair scheduling and the algorithm P-ERfair-PD2 which applies Pfair modifications used for Partly-Pfair on the concept of ERfairness and PD2 policies. With a simulation based schedulability examination we show for multiple time base (MTB) task sets that P-ERfair- PD2 has the same performance as Partly-Pfair-PD2. Additionally, we show that P-ERfair- PD2 has a much higher robustness against perturbations, and therefore it is well suited for embedded domains, especially for the Automotive domain. Y1 - 2010 UR - https://www.researchgate.net/publication/287883010_Efficient_scheduling_of_reliable_automotive_multi-core_systems_with_pd2_by_weakening_erfair_tasksystem_requirements SP - 53 EP - 67 ER - TY - JOUR A1 - Deubzer, Michael A1 - Schiller, Frank A1 - Mottok, Jürgen A1 - Niemetz, Michael A1 - Margull, Ulrich T1 - Effizientes Multicore-Scheduling in Eingebetteten Systemen – Teil 1: Algorithmen für zuverlässige Echtzeitsysteme JF - atp - Automatisierungstechnische Praxis N2 - Eingebettete Systeme unterliegen neben den funktionalen Anforderungen besonders nicht funktionalen Qualitätsanforderungen wie Effizienz, Zuverlässigkeit und Echtzeitfähigkeit. Mit steigendem Bedarf an Rechenkapazität können bisherige Konzepte zur Leistungssteigerung von Singlecore-Systemen jedoch nicht mehr eingesetzt werden – der Umstieg auf Multicore-Systeme wird erforderlich. Im ersten Teil dieser Arbeit werden eine mögliche Prozessorarchitektur für zukünftige Automotive Multicore-Systeme und die Abstraktion der Software für diese Systeme vorgestellt. Nach einer Klassifkation von Multicore-Scheduling-Algorithmen präsentieren wir exemplarisch einen Algorithmus mit statischer Taskallokation und einen Algorithmus mit dynamischer Taskallokation. Bei beiden Algorithmen handelt es sich um eine Überführung theoretisch behandelter Algorithmen auf Automotive Systeme. Y1 - 2010 UR - https://docplayer.org/4474533-Effizienter-einsatz-von-multicore-systemen.html IS - 9 SP - 60 EP - 67 ER - TY - CHAP A1 - Schorer, Michael A1 - Kuntz, Stefan A1 - Mottok, Jürgen T1 - Verification of Behavioral Compatibility in the Virtual Integration Methodology T2 - 8th IEEE Workshop on Intelligent Solutions in Embedded Systems,Heraklion, Greece, July 2010 N2 - The advantages of component-based systems include reuse of generic components as well as adaption through variants. However, they bare a high risk of containing incompatibilities between components, due to the lack of control over the integration-relevant aspects of their components. Current development processes are able to detect incompatibilities between components only at very late stages of system development. The Virtual Integration methodology is an approach to detect and to solve compatibility issues during early stages of system design. The methodology supports developers with a set of measures to reduce the risk of incompatibilities to a minimum at each abstraction layer of their system architecture. Realtime requirements of embedded systems make it necessary to support the methodology with a formal model, which can describe dynamic properties of these systems. In our approach, we use interface automata because they offer a lightweight formalism to describe the behavior of components and to verify their compatibility based on these descriptions. In a feasibility study we show, to which extend interface automata are adequate for the foresaid purpose in the automotive application field. Y1 - 2010 U6 - https://doi.org/10.1109/WISES.2010.5548424 SP - 35 EP - 42 ER - TY - JOUR A1 - Deubzer, Michael A1 - Schiller, Frank A1 - Mottok, Jürgen A1 - Niemetz, Michael A1 - Margull, Ulrich T1 - Effizientes Multicore-Scheduling in Eingebetteten Systemen – Teil 2: Ein simulationsbasierter Ansatz zum Vergleich von Scheduling-Algorithmen JF - atp - Automatisierungstechnische Praxis N2 - Eingebettete Systeme unterliegen neben den funktionalen Anforderungen besonders nichtfunktionalen Qualitätsanforderungen wie Effizienz, Zuverlässigkeit und Echtzeitfähigkeit. Mit steigendem Bedarf an Rechenkapazität können bisherige Konzepte zur Leistungssteigerung von Singlecore-Systemen jedoch nicht mehr eingesetzt werden - der Umstieg auf Multicore-Systeme wird erforderlich. Im zweiten Teil dieser Arbeit wird ein simulationsbasierter Ansatz zum Vergleich von Multicore-Scheduling-Algorithmen vorgestellt, mit dem Algorithmen für Multicore-Systeme mit voller Migration und dynamischer Task-Priorität untersucht werden. Wir erweitern diesen Ansatz um ein Verfahren zur Untersuchung einer Tasksetmenge mit stochastisch beschriebenen Eigenschaften und vergleichen ihn mit den im Teil 1 beschriebenen Algorithmen BinPacking-EDF und P-ERfair-PD² für eine Gruppe von Automotive Powertrain Systemen. Y1 - 2010 VL - 52 IS - 10 ER - TY - CHAP A1 - Deubzer, Michael A1 - Margull, Ulrich A1 - Mottok, Jürgen A1 - Niemetz, Michael A1 - Wirrer, Gerhard T1 - Partly Proportionate Fair Multiprocessor Scheduling of Heterogeneous Task Systems T2 - 5th Embedded Real Time Software and Systems Conference, May 2010 N2 - Proportionate fair (Pfair) scheduling, which allows task migration at runtime and assigns each task processing time with regard to its weight, is one of the most efficient group of SMP multiprocessor scheduling algorithms known up to now. Drawbacks are tight requirements to the task system, namely the restriction to periodic task systems with synchronized task activation, quantized task execution time, and implicit task deadline. Most likely, a typical embedded real-time system does not fulfill these requirements. In this paper we address violations of these requirements. For heterogeneous task systems, we define the multiple time base (MTB) task system, which is a less pessimistic model than sporadic task systems and is used for automotive systems. We apply the concept of Pfair scheduling to MTB task systems, called partly proportionate fair (Partly-Pfair) scheduling. The restrictions on MTB task systems required for Partly-Pfair ness are weaker than restrictions on periodic task systems required for Pfair ness. In a simulation based study we examined the performance of Partly-Pfair-PD and found it capable to schedule feasible MTB task sets causing a load of up to 100% of the system capacity. Y1 - 2010 ER - TY - CHAP A1 - Bärwald, Andreas A1 - Hauff, Harald A1 - Mottok, Jürgen T1 - Qualification and Certification of Development Tools for Safety-Critical Applications T2 - Automotive Safety & Security N2 - This paper presents an overview on qualification and certification of tools used in the phases of the safety lifecycle for safety-critical applications, either for development or for verification and validation. Software development tools are widely used in the development of safety-critical software systems. More verification and validation procedures will be automated by software tools to reduce time consuming manual testing. The impact of software tools on functional safety is discussed. Based on normative regulations like IEC 61508 and ISO DIS 26262 different approaches for tool qualification and certification are presented. Y1 - 2010 UR - https://www.researchgate.net/publication/289001902_Qualification_and_certification_of_development_tools_for_safety-critical_applications SP - 135 EP - 149 ER - TY - CHAP A1 - Steindl, Michael A1 - Mottok, Jürgen A1 - Meier, Hans T1 - SES-based Framework for Fault-tolerant Systems T2 - 8th IEEE Workshop on Intelligent Solutions in Embedded Systems, Heraklion, Greece, July 2010 N2 - Embedded real-time systems are often used in harsh environments, for example engine control systems in automotive vehicles. In such ECUs (Engine Control Unit) faults can lead to serious accidents. In this paper we propose a safety embedded architecture based on coded processing. This framework only needs two channels to provide fault tolerance and allows the detection and identification of permanent and transient faults. Once a fault is detected by an observer unit the SES guard makes it visible and initiates a suitable failure reaction. Y1 - 2010 U6 - https://doi.org/10.1109/WISES.2010.5548427 SP - 12 EP - 16 ER - TY - JOUR A1 - Bärwald, Andreas A1 - Hauff, Harald A1 - Mottok, Jürgen T1 - Certification of safety relevant systems – Benefits of using pre-certified components JF - Automotive Safety and Security Y1 - 2010 ER - TY - CHAP A1 - Stappert, Friedhelm A1 - Jonsson, Jan A1 - Mottok, Jürgen A1 - Johansson, Rolf T1 - A Design Framework for End-to-End Timing Constrained Automotive T2 - 5th Embedded Real Time Software and Systems Conference (ERTS2 2010), May 2010, Toulouse, France Y1 - 2010 UR - https://hal.archives-ouvertes.fr/hal-02264378 ER - TY - CHAP A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Osek-basierende Implementierung des LLREF-Scheduling-Algorithmus für eine Dual-Core-Architektur T2 - 2. Landshuter Symposium Mikrosystemtechnik, Tagungsband, 24. une 25. Februar 2010, Hochschule Landshut Y1 - 2010 SP - 343 EP - 349 ER - TY - CHAP A1 - Steindl, Michael A1 - Mottok, Jürgen A1 - Meier, Hans A1 - Schiller, Frank A1 - Früchtl, M. T1 - Safeguarded Processing of Sensor Data T2 - 5th Embedded Real Time Software and Systems Conference (ERTS2 2010), May 2010, Toulouse, France Y1 - 2010 ER - TY - CHAP A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Cyclic codes and error detection during data processing in embedded software systems T2 - Proceedings of the 4rd Embedded Software Engineering Congress (ESE), 5.-9. Dezember 2011, Sindelfingen Y1 - 2011 SP - 577 EP - 590 ER - TY - JOUR A1 - Bärwald, Andreas A1 - Hauff, Harald A1 - Mottok, Jürgen T1 - Qualifizierung und Zertifizierung von Software-Entwicklungswerkzeugen JF - Hanser Automotive Y1 - 2010 SP - 34 EP - 39 ER - TY - JOUR A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Multi-Core Scheduling in Embedded Systemen, Teil 1 JF - Hanser Automotive Y1 - 2010 IS - 1-2 SP - 18 EP - 22 ER - TY - JOUR A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Multi-Core Scheduling in Embedded Systemen, Teil 2 JF - Hanser Automotive Y1 - 2010 IS - 3-4 SP - 23 EP - 25 ER - TY - JOUR A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Multi-Core Scheduling in Embedded Systemen, Teil 3 JF - Hanser Automotive Y1 - 2010 IS - 5-6 SP - 14 EP - 16 ER - TY - CHAP A1 - Mottok, Jürgen A1 - Gardeia, Armin T1 - The regensburg concept of p-seminars – how to organize the interface between secondary school and university education to create a didactic cooperation between teaching and learning of software engineering with lego mindstorms nxt embedded robot systems T2 - 2011 IEEE Global Engineering Education Conference (EDUCON), Amman, Jordan, 2011 N2 - This paper describes the background and the theory of the learning arrangement “The Regensburg Concept of P 1 - Seminars” and its potential fields of application. This conception was designed to meet the various requirements caused by the Bologna Accords and the restructuring of the senior years of German secondary school education. At the same time it aims at finding solutions for a severe problem topical in Germany: the lack of students qualifying in MINT (the fields of mathematics, informatics, natural sciences and techniques.) The focus of this conception is on the cooperation between universities and schools hence a draft of the P-Seminar has already been realized and evaluated during a pilot phase at a local secondary school. These experiences serve as a solid basis for the development of a concrete plan that makes it possible to transfer the concept to similar projects in future. In the following paragraphs keywords that are applied to the lexical field of the Regensburg Concept are elaborated e.g. "practive learning", an interaction of practical and active learning. Y1 - 2011 U6 - https://doi.org/10.1109/EDUCON.2011.5773255 SP - 917 EP - 920 ER - TY - CHAP A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans A1 - Racek, Stanislav T1 - Safe software processing by concurrent execution in a real-time operating system T2 - 16th International Conference on Applied Electronics (AE 2011), 2011, Pilsen, Czech Republic N2 - The requirements for safety-related software systems increases rapidly. To detect arbitrary hardware faults, there are applicable coding mechanism, that add redundancy to the software. In this way it is possible to replace conventional multi-channel hardware and so reduce costs. Arithmetic codes are one possibility of coded processing and are used in this approach. A further approach to increase fault tolerance is the multiple execution of certain critical parts of software. This kind of time redundancy is easily realized by the parallel processing in an operating system. Faults in the program flow can be monitored. No special compilers, that insert additional generated code into the existing program, are required. The usage of multi-core processors would further increase the performance of such multi-channel software systems. In this paper we present the approach of program flow monitoring combined with coded processing, which is encapsulated in a library of coded data types. The program flow monitoring is indirectly realized by means of an operating system. Y1 - 2011 SP - 315 EP - 319 ER - TY - CHAP A1 - Braun, Jürgen A1 - Mottok, Jürgen A1 - Miedl, Christian A1 - Geyer, Dirk A1 - Minas, Mark T1 - Overview and Evaluation of Fail-Safe and Fault-Tolerant Mechanisms for the Electromobility according to ISO26262 T2 - 1st International Electromobility Congress, 12. - 13. 5. 2011, Prague Y1 - 2011 ER - TY - CHAP A1 - Schmidhuber, Stefan A1 - Deubzer, Michael A1 - Mottok, Jürgen T1 - Parallelisierte Echtzeitanalyse von Eingebetteten Systemen T2 - Proceedings of the 4rd Embedded Software Engineering Congress (ESE), 5.-9. Dezember 2011, Sindelfingen Y1 - 2011 SP - 516 EP - 524 ER - TY - CHAP A1 - Mottok, Jürgen T1 - Storytelling: Finite state machines Lernen leicht gemacht! T2 - Proceedings of the 4rd Embedded Software Engineering Congress (ESE), 5.-9. Dezember 2011, Sindelfingen Y1 - 2011 ER - TY - CHAP A1 - Mottok, Jürgen T1 - General purpose computing on graphics processing unit by using cuda T2 - Applied Research Conference 2011 (ARC 2011), 6. April, Regensburg Y1 - 2011 ER - TY - CHAP A1 - Mottok, Jürgen T1 - Ses and the iso 26262 T2 - Applied Research Conference 2011 (ARC 2011), 6. April, Regensburg Y1 - 2011 ER - TY - CHAP A1 - Lalo, Erjola A1 - Deubzer, Michael A1 - Schmidhuber, Stefan A1 - Oklapi, Erna A1 - Mottok, Jürgen T1 - Task Priority Optimization in Real-Time Multi-Core Embedded Systems T2 - 4. Landshuter Symposium Mikrosystemtechnik, Mikrosystemtechnik als Schlüsseltechnologie der Systemintegration, Tagungsband zum Symposium 12./13. März 2014, Hochschule Landshut N2 - The shift from single-core to multi-core processors in real-time embedded systems leads to communication based effects on timing such as inter-core communication delays and blocking times. Moreover, the complexity of the scheduling problem increases when multi-core processors are used. In priority-based-scheduling, a fixed priority assignment is used in order to enable predictable behavior of the system. Predictability means that the system has to be analyzable which allows the detection of problems coming from scheduling decisions. For fixed priority scheduling in multi-core real-time embedded systems, a proper task priority assignment has to be done in a way that the system has minimal effects on timing. In this paper, we present an approach for finding near-optimal solutions for task priority assignment and the preemption/cooperation problem. A genetic algorithm is hereby used to create priority assignment solutions. A timing simulator is used for evaluation of each solution regarding real-time properties, memory consumption and communication overhead. In a case study we demonstrate that the proposed approach performs better than well known and single-core optimal heuristics for relatively complex systems. Y1 - 2014 SN - 978-3-9812696-5-9 SP - 96 EP - 109 CY - Landshut ER - TY - CHAP A1 - Altmann, Andreas A1 - Birkner, Wolfgang A1 - Häckl, Franz-Xaver A1 - Hanner, Christopher A1 - Liebhart, Peter A1 - Metschl, Samuel A1 - Weck, Florian A1 - Farmbauer, Michael A1 - Heiß, Manfred A1 - Cuno, H.-H. A1 - Fuhrmann, Thomas A1 - Mandl, Roland A1 - Mottok, Jürgen A1 - Niemetz, Michael T1 - Payload development and launch of a stratosphere balloon mission T2 - IEEE Global Engineering Education Conference (EDUCON 2014), 3-5 April 2014, Istanbul, Turkey N2 - During a student project a stratosphere balloon was developed and launched. This project included the definition of the balloon parameters and the scientific instruments for performing atmospheric measurements, the development of all mechanical and electronic parts, the administration of the project as well as the management tasks related to the balloon launch. The main challenge for the students was the high complexity of the project due to tasks involving many different knowledge domains and the long project duration from the initial definition to the launch. Y1 - 2014 U6 - https://doi.org/10.1109/EDUCON.2014.6826065 ER - TY - JOUR A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Vavricka, Vlastimil T1 - Isomorphism between Linear Codes and Arithmetic Codes for Safe Data Processing in Embedded Software Systems JF - Computing and Informatics (CAI) N2 - We present a transformation rule to convert linear codes into arithmetic codes. Linear codes are usually used for error detection and correction in broadcast and storage systems. In contrast, arithmetic codes are very suitable for protection of software processing in computer systems. This paper shows how to transform linear codes protecting the data stored in a computer system into arithmetic codes safeguarding the operations built on this data. Combination of the advantages of both coding mechanisms will increase the error detection capability in safety critical applications for embedded systems by detection and correction of arbitrary hardware faults. Y1 - 2014 UR - https://pdfs.semanticscholar.org/eb7c/f626eb4dcf33bb9c615d477099188eadc76b.pdf?_ga=2.23977850.1374482597.1614464499-73487869.1612391519 VL - 33 SP - 721 EP - 734 ER - TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen A1 - Racek, Stanislav T1 - Comparison of Enhanced Markov Models and Discrete Event Simulation T2 - 17th Euromicro Conference on Digital System Design (DSD), 27-29 August 2014, Verona, Italy N2 - In this paper we present simulation and model based approaches for evaluating and validating the temporal and safety relevant properties of software intensive safety-critical real-time embedded systems. A high level reliability model of a safe task execution is described by a continuous-time Markov process, enhanced by the modeling of execution times. It is shown that the behavior - regarding real-time and safety metrics - of this theoretical model can be transferred into an abstract system timing model, which then can be analyzed by a discrete event simulation approach. The verification of the discrete event simulation by Markov models offers the possibility of a holistic approach for reliability analysis combined with schedulability analysis of complex safety-critical multicore real-time systems by the discrete event simulation. Y1 - 2014 U6 - https://doi.org/10.1109/DSD.2014.42 SP - 591 EP - 598 ER - TY - CHAP A1 - Mottok, Jürgen A1 - Scharfenberg, Georg T1 - Forschendes Lernen im Masterstudiengang Applied Research in Engineering Sciences T2 - 4th Applied Research Conference, 5th July 2014, Ingolstadt Y1 - 2014 SN - 978-3-8440-2875-1 SP - 55 EP - 61 PB - Shaker CY - Aachen ER - TY - CHAP A1 - Scharfenberg, Georg A1 - Mottok, Jürgen T1 - Forschungsmaster entwickelt sich zum Wirtschaftsfaktor in Bayern T2 - 4th Applied Research Conference, 5th July 2014, Ingolstadt Y1 - 2014 SN - 978-3-8440-2875-1 SP - 55 EP - 61 PB - Shaker CY - Aachen ER - TY - GEN A1 - Weiss, Nils T1 - Reverse Engineering and Weaponizing OBD Dongles T2 - Automotive Security Research Group, Stuttgart, Germany 2019, Meeting 22 Y1 - 2019 UR - https://www.meetup.com/de-DE/Automotive-Security-Research-Group-ASRG/events/261796924/ ER - TY - CHAP A1 - Gschossmann, Andreas A1 - Jobst, Simon A1 - Mottok, Jürgen A1 - Bierl, Rudolf T1 - A Measure of Confidence of Artificial Neural Network Classifiers T2 - ARCS Workshop 2019; 32nd International Conference on Architecture of Computing Systems, 20-21 May 2019, Copenhagen, Denmark N2 - Confidence in results of an Artificial Neural Networks (ANNs) is increased by preferring to reject data, that is not trustful, instead of risking a misclassification. For this purpose a model is proposed that is able to recognize data, which differs significantly from the training data, during inference. The proposed model observes all activations of the hidden layers, as well as input and output layers of an ANN in a grey-box view. To make ANNs more robust in safety critical applications, this model can be used to reject flawed data, that is suspected to decrease the accuracy of the model. If this information is logged during inference, it can be used to improve the model, by training it specifically with the missing information. An experiment on the MNIST dataset is conducted and its results are discussed. Y1 - 2019 UR - https://ieeexplore.ieee.org/document/8836211 SP - 153 EP - 157 PB - VDE-Verlag CY - Berlin ER - TY - CHAP A1 - Schmidhuber, Stefan A1 - Deubzer, Michael A1 - Mader, Ralph A1 - Niemetz, Michael A1 - Mottok, Jürgen T1 - Towards the Derivation of Guidelines for the Deployment of Real-Time Tasks on a Multicore Processor T2 - 4th International Symposium on Model-Based Safety and Assessment (IMBSA 2014), Munich, Germany, October 27-29, 2014, Proceedings N2 - The deployment of automotive software on a multicore processor includes the task of mapping executables to cores. Given the number of possible solutions, integrators have to solve a complex problem. Considering multiple, often conflicting goals like minimizing task response times and memory consumption, complexity further increased with the advent of multicore processors. We present a model-based approach for deriving design rules supporting integrators with statically mapping tasks to a multicore ECU. First, an evolutionary algorithm is used to sample the design space. For each sample, a model-based analysis is performed, resulting in the required fitness values according to the system metric objectives. Finally, subsets of the sample population are used to derive deployment guidelines by evaluating similarities between highly ranked solutions. This reduces the number of solutions to be considered by the integrators by orders of magnitude. In a case-study, we demonstrate the developed approach on an artificial automotive engine management system. KW - Real-time systems KW - embedded multicore systems KW - runnable partitioning KW - task-to-core mapping KW - software integration KW - design space exploration KW - evolutionary algorithm Y1 - 2014 SN - 978-3-319-12213-7 U6 - https://doi.org/10.1007/978-3-319-12214-4_12 SP - 152 EP - 165 PB - Springer CY - Munich ER - TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen A1 - Racek, Stanislav T1 - Comparison of Enhanced Markov Models and Discrete Event Simulation – for evaluation of probabilistic Faults in safety-critical real-time task sets T2 - Proceedings of EUROMICRO DSD 2014 - 17th Euromicro Conference on Digital System Design N2 - In this paper we present simulation and model based approaches for evaluating and validating the temporal and safety relevant properties of software intensive safety-critical real-time embedded systems. A high level reliability model of a safe task execution is described by a continuous-time Markov process, enhanced by the modeling of execution times. It is shown that the behavior - regarding real-time and safety metrics - of this theoretical model can be transferred into an abstract system timing model, which then can be analyzed by a discrete event simulation approach. The verification of the discrete event simulation by Markov models offers the possibility of a holistic approach for reliability analysis combined with schedulability analysis of complex safety-critical multicore real-time systems by the discrete event simulation. KW - Model KW - Stochastic simulation KW - reliability analysis KW - safe software processing KW - real-time operating system KW - multicore scheduling KW - discrete event simulation KW - fault injection Y1 - 2014 U6 - https://doi.org/10.1109/DSD.2014.42 SP - 591 EP - 598 ER - TY - CHAP A1 - Alfranseder, Martin A1 - Deubzer, Michael A1 - Justus, Benjamin A1 - Mottok, Jürgen A1 - Siemers, Christian T1 - An Efficient Spin-Lock Based Multi-Core Resource Sharing Protocol T2 - 33rd IEEE International Performance, Computing, and Communications Conference (IPCCC), Austin (TX), USA, 5-7 December 2014 N2 - We present in this paper a new lock-based resource sharing protocol PWLP (Preemptable Waiting Locking Protocol) for embedded multi-core processors. It is based on the busy-wait model and works with non-preemptive critical sections while task may be preempted by tasks with a higher priority when waiting for resources. Our protocol can be applied in partitioned as well as global scheduling scenarios, in which task-fix, job-fix or dynamically assigned priorities may be used. Furthermore, the PWLP permits nested requests to shared resources. Finally, we present a case study based on event-based simulations in which the FMLP (Flexible Multiprocessor Locking Protocol) and the proposed PWLP are compared. Y1 - 2014 U6 - https://doi.org/10.1109/PCCC.2014.7017090 ER - TY - CHAP A1 - Alfranseder, Martin A1 - Krapf, Tobias A1 - Mader, Ralph A1 - Niemetz, Michael A1 - Mottok, Jürgen A1 - Siemers, Christian T1 - An Efficient Partitioning Strategy for Runnables in Weakly Dependent Tasks on Embedded Multi-Core Systems T2 - Embedded real-time software and systems (ERTS² 2014), Feb 2014, Toulouse, France N2 - With multi-core controllers entering the area of automotive control ECUs, strategies for parallelizing the control- algorithms come into focus. This paper deals with a special part of automotive powertrain software, called state transitions. Since dependencies between runnables executed there are weak, the transitions provide a good basis for parallelization. We present a strategy of how to distribute efficiently the execution of runnables to different cores while taking care of inner and outer dependencies. The strategy is accompanied by two case studies demonstrating the performance of the concept. The first one is carried out to find the most efficient strategies of parallelize state transitions based on randomly generated, simulated state transitions. In the second one, the developed partitioning strategies are applied to a real software project for an automotive powertrain system. Y1 - 2014 ER - TY - CHAP A1 - Helm, C. A1 - Deubzer, Michael A1 - Mottok, Jürgen ED - Ivanov, Artem ED - Bicker, Marc ED - Patzelt, Peter T1 - Analyse der Echtzeiteigenschaften von Multicore Speicherarchitekturen in Eingebetteten Systemen mittels einer konfigurierbaren Simulationssoftware T2 - 4. Landshuter Symposium Mikrosystemtechnik : Mikrosystemtechnik als Schlüsseltechnologie der Systemintegration, Tagungsband zum Symposium 12./13. März 2014, Hochschule Landshut Y1 - 2014 SN - 978-3-9812696-5-9 SP - 109 EP - 117 CY - Landshut ER - TY - CHAP A1 - Lalo, Erjola A1 - Schmidhuber, Stefan A1 - Deubzer, Michael A1 - Mottok, Jürgen T1 - Extended Task Priority and Preemptability Optimization in Real-Time Multi-Core Embedded Systems T2 - 4th Applied Research Conference, 5th July 2014, Ingolstadt Y1 - 2014 SN - 978-3-8440-2875-1 SP - 90 EP - 95 CY - Ingolstadt ER - TY - CHAP A1 - Thiel, P. A1 - Hackl, Magnus A1 - Mottok, Jürgen T1 - Designing efficient Node.js applications – Approaching useful patterns T2 - 4th Applied Research Conference, 5th July 2014, Ingolstadt Y1 - 2014 SN - 978-3-8440-2875-1 SP - 40 EP - 46 PB - Shaker CY - Aachen ER - TY - CHAP A1 - Hackl, Magnus A1 - Thiel, Patrik A1 - Mottok, Jürgen T1 - Not Only SQL – a comparison to traditional RDBMS T2 - 4th Applied Research Conference (ARC 2014), 5th July 2014, Ingolstadt Y1 - 2014 SN - 978-3-8440-2875-1 PB - Shaker CY - Aachen ER - TY - CHAP A1 - Raab, Peter A1 - Mottok, Jürgen T1 - Modellbasierte Zuverlässigkeitsanalysen von arithmetischen Operationen in einem Prozessorsystem T2 - Proceedings of safe.tech 2014, 20. und 21. Mai 2014, München Y1 - 2014 ER - TY - CHAP A1 - Figas, Paula A1 - Knörl, Susanne A1 - Mörtlbauer, Stefanie A1 - Sedelmaier, Yvonne A1 - Schroll-Decker, Irmgard ED - Hagel, Georg ED - Mottok, Jürgen T1 - Developing Software Engineering Education as a Didactical Discipline in its own right T2 - 1st European Conference on Software Engineering Education (ECSEE) at Seon Monastery, Germany N2 - Simultaneously to the growing significance of the discipline software engineering (SE) also its education becomes more important. This reinforces the need of a theoretical foundation of software engineering education, but there is still a lack of scientifically justified didactical concepts. In the context of the project EVELIN (Experimental Improvement in Learning Software Engineer-ing) the authors want to give a decisive impulse for the development of a “Fachdidaktik software engineering” (FD-SE). In order to compile an adequate theoretical basis for a Fachdidaktik of software engineering “Allgemeine Did-aktik” (AD)1, its relation to “Fachdidaktik” (FD) in general, the special branch of science of software engineering and related scientific disciplines are dis-cussed. This analysis is used to justify the necessity of an autonomous scientific discipline Fachdidaktik software engineering which meets the challenges of teaching and learning software engineering. The main contributions of this pa-per are proposals on how this FD can be built scientifically upon AD, on the one hand, and how it can be implemented by specific didactical approaches for software engineering, on the other hand. KW - Fachdidaktik KW - Software Engineering KW - Lehre KW - Hochschule Y1 - 2014 UR - https://www.researchgate.net/publication/269762126_Developing_Software_Engineering_Education_as_a_Didactical_Discipline_in_its_own_right SP - 1 EP - 15 PB - Shaker Verlag ER - TY - CHAP A1 - Oklapi, Erna A1 - Deubzer, Michael A1 - Schmidhuber, Stefan A1 - Lalo, Erjola A1 - Mottok, Jürgen T1 - Optimization of Real-Time Multicore Systems Reached by a Genetic Algorithm Approach for Runnable Sequencing T2 - 2014 International Conference on Applied Electronics, Pilsen, Czech Republic N2 - The deployment of complex real-time systems with everyday increasing demands and possibilities, is a challenging task for engineers when performance and efficiency have to be maximized while cost have to be minimized at the same time. For already designed systems it became necessary to perform different modifications in order to find optimal software architecture configuration by respecting all timing constraints which are essential when speaking of real-time systems. In this work, we present a model-based approach of optimizing the execution sequence of runnables within tasks in order to reduce the system's reaction times by improving the overall signal flow duration. Hereby, a genetic optimization algorithm is used to create and evaluate multiple solutions for the runnable sequencing problem. We conclude by demonstration the efficiency of the presented approach with experimental results. KW - runnable sequencing KW - embedded real-time systems KW - genetic algorithms KW - multi-core KW - optimization Y1 - 2014 U6 - https://doi.org/10.1109/AE.2014.7011709 SP - 233 EP - 238 ER - TY - CHAP A1 - Mottok, Jürgen A1 - Alfranseder, Martin A1 - Schmidhuber, Stefan A1 - Mucha, Matthias A1 - Sailer, Andreas ED - Teodorescu, Horia-Nicolai ED - Kirschenbaum, Alan ED - Cojocaru, Svetlana ED - Bruderlein, Claude T1 - How to improve the reactiveness and efficiency of embedded multicore systems by use of probabilistic simulation and optimization techniques T2 - Improving Disaster Resilience and Mitigation - New Means and Tools. NATO Science for Peace and Security Series C: Environmental Security N2 - Safe and reliable multi-core technology becomes more and more important in the field of embedded systems. Today’s and future embedded systems require increasing performance while being more energy efficient. Moreover, the functional safety for these embedded systems has to be improved or developed completely new. In this chapter, we first address the challenges of embedded multi-core real-time systems. To raise the resilience of such systems we use the deadlock-free synchronization model of Block et al. (A flexible real-time locking protocol for multiprocessors. 2012 IEEE international conference on embedded and real-time computing systems and applications, vol 0, pp 47–56, 2007). The metric mean Normalized Blocking Time (mNBT) is hereby used to measure the timing effects of the blocking behavior of strongly interacting tasks. In a second step, we present a model-based approach to map the tasks of an embedded real-time system to the cores of a multi-core processor. Moreover, we derive an execution time model from runtime measurements of software functions. This information is then used to perform precise probabilistic simulations of different task-to-core mappings and evaluate them with regard to task response times, inter-task blocking overhead and load distribution. Subsequently, we integrate the probabilistic simulation within an optimization technique to systematically improve the task-to-core mapping. We conclude with a case-study, where we demonstrate the effectiveness of the presented approach by optimizing the task-to-core mapping of a practical automotive powertrain system. KW - Embed System KW - Functional Safety KW - Arrival Curve KW - Task Allocation Problem KW - Deadline Violation Y1 - 2014 U6 - https://doi.org/10.1007/978-94-017-9136-6_16 SP - 253 EP - 268 PB - Springer CY - Dodrecht ER - TY - CHAP A1 - Braun, Jürgen A1 - Mottok, Jürgen T1 - Fail-Safe and Fail-Operational Systems safeguarded with Coded Processing T2 - 2013 IEEE EUROCON - International Conference on Computer as a Tool, Zagreb, Croatia, July 1-4, 2013 N2 - Safety has the highest priority because it helps contribute to customer confidence and thereby ensures further growth of the new markets, like electromobility. Therefore in series production redundant hardware concepts like dual core microcontrollers running in lock-step-mode are used to reach for example ASIL D safety requirements given from the ISO 26262. Coded processing is capable of reducing redundancy in hardware by adding diverse redundancy in software, e.g. by specific coding of data and instructions. A system with two coded processing channels is considered. Both channels are active. When one channel fails, the service can be continued with the other channel. It is imaginable that the two channels with implemented coded processing are running with time redundancy on a single core or on a multi core system where for example different ASIL levels are partitioned on different cores. In this paper a redundancy concept based on coded processing will be taken into account. The improvement of the Mean Time To Failure by safeguarding the system with coded processing will be computed for fail-safe as well as for fail-operational systems. The use of the coded processing approach in safeguarding failsafe systems is proved. KW - fail-safe KW - fail-operational KW - fault-tolerant KW - failure probability KW - coded processing KW - Safely Embedded Software KW - SES KW - safety measure KW - ISO 26262 KW - electromobility KW - Mean Time To Failure KW - MTTF KW - reliability KW - diversity Y1 - 2013 SN - 978-1-4673-2231-7 U6 - https://doi.org/10.1109/EUROCON.2013.6625234 SP - 1878 EP - 1885 ER - TY - CHAP A1 - Soska, Alexander A1 - Mottok, Jürgen T1 - A New Conceptual Contribution for Serious Games in Academic Software Engineering Education T2 - European Conference on Software Engineering Education 2014 (ECSEE), 27 and 28 November 2014 in Seeon Monastery N2 - Nowadays, the popularity and field of application of serious games grows steadily. This educational method offers attractive pportunities for teaching and training by combining playful elements with learning content. By using game mechanics, thinking and technique, theoretical subject matters are treated in a fun and engaging way. Thereby, serious games utilize our intrinsic motivation to discover the surroundings in a playful manner. Embedded in educational settings, the goal is to mediate academic and non-academic knowledge to the students. Especially in the field of software engineering it is important to have skills which go beyond pure technical knowledge. Yet, the use of serious games is still a manageable amount. With this paper, we give a contribution to the theoretical design and development of serious games based on playful learning method and its relation to research-based learning in universal context. In addi- tion we analyze the existing serious games in software engineering and present our thoughts about planning our own. Y1 - 2014 UR - https://www.researchgate.net/publication/277266392_A_New_Conceptual_Contribution_for_Serious_Games_in_Academic_Software_Engineering_Education SN - 978-3-8440-3067-9 SP - 241 EP - 254 PB - Shaker CY - Aachen ER - TY - CHAP A1 - Alfranseder, Martin A1 - Mucha, Matthias A1 - Schmidhuber, Stefan A1 - Sailer, Andreas A1 - Niemetz, Michael A1 - Mottok, Jürgen T1 - A modified synchronization model for dead-lock free concurrent execution of strongly interacting task sets in embedded systems T2 - 2013 International Conference on Applied Electronics (AE 2013), IEEE, 10-12 September 2013, Pilsen, Czech Republic N2 - Global scheduling algorithms are very promising for application in embedded real-time systems using multi-core controllers. In this paper we want to make a first step forward to apply such scheduling methods on real existing systems. Especially a new resource model is necessary to avoid deadlocks, as this goal can not be achieved by using the standard OSEK Priority Ceiling Protocol when shared global resources are in use. We also introduce the new metric mean Normalized Blocking Time in order to be able to compare locking mechanisms according to the timing effects of their blocking behavior. Finally we give a simulative application example of the new metric by the use of two different kinds of semaphore models and an example task set typical for existing embedded real-time systems in the automotive powertrain environment. Y1 - 2013 VL - 18 SP - 13 EP - 18 ER - TY - CHAP A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Error Model and the Reliability of Arithmetic Operations T2 - 2013 IEEE EUROCON - International Conference on Computer as a Tool, Zagreb, Croatia, July 1-4, 2013 N2 - Error detecting and correcting codes are widely used in data transmission, storage systems and also for data processing. In logical circuits like arithmetic operations, arbitrary faults can cause errors in the result. However in safety critical applications, it is important to avoid those errors which would lead to system failures. Several approaches are known to protect the result of operations during software processing. In the same way like transmission systems, coded processing uses codes for fault detection. But in contrast to transmission systems, there is no adequate channel model available which makes it possible to evaluate the residue error probability of an arithmetic operation in an analytical way. This paper tries to close the gap of arithmetic error models by the development of a model for an ordinary addition in a computer system. Thus, the reliability of an addition's result can be analytically evaluated. KW - addition KW - channel model KW - coded processing KW - fault simulation KW - Markov model KW - residue error probability Y1 - 2013 U6 - https://doi.org/10.1109/EUROCON.2013.6625047 SP - 630 EP - 637 ER - TY - CHAP A1 - Raab, Peter A1 - Racek, Stanislav A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Data Flow Analysis of Software Executed by Unreliable Hardware T2 - 16th Euromicro Conference on Digital System Design, Los Alamitos, CA, USA N2 - The data flow is a crucial part of software execution in recent applications. It depends on the concrete implementation of the realized algorithm and it influences the correctness of a result in case of hardware faults during the calculation. In logical circuits, like arithmetic operations in a processor system, arbitrary faults become a more tremendous aspect in future. With modern manufacturing processes, the probability of such faults will increase and the result of a software's data flow will be more vulnerable. This paper shows a principle evaluation method for the reliability of a software's data flow with arbitrary soft errors also with the concept of fault compensation. This evaluation is discussed by means of a simple example based on an addition. KW - data flow KW - error probability KW - fault compensation KW - reliability analysis KW - software-implemented-hardwarefault-tolerance (SIHFT) Y1 - 2013 U6 - https://doi.org/10.1109/DSD.2013.35 SP - 243 EP - 249 ER - TY - CHAP A1 - Oklapi, Erna A1 - Deubzer, Michael A1 - Schmidhuber, Stefan A1 - Mottok, Jürgen T1 - Verification of an Evolutionary Optimization Algorithm for Runnable Sequencing Problem T2 - 4th Applied Research Conference, 5th July 2014, Ingolstadt Y1 - 2014 ER - TY - CHAP A1 - Alfranseder, Martin A1 - Krapf, Tobias A1 - Mottok, Jürgen A1 - Siemers, Christian T1 - Synchronisationsverfahren in embedded Multicoresystemen T2 - Tagungsband, 6th Embedded Software Engineering, Kongress 2013, 2. bis 6. Dezembern 2013, Sindelfingen Y1 - 2013 PB - Vogel Business Media CY - Würzburg ER - TY - CHAP A1 - Sailer, Andreas A1 - Schmidhuber, Stefan A1 - Deubzer, Michael A1 - Alfranseder, Martin A1 - Mucha, Matthias A1 - Mottok, Jürgen T1 - Optimizing the task allocation step for multi-core processors within autosar T2 - 2013 International Conference on Applied Electronics, IEEE, Pilsen, Czech Republic N2 - We present a model-based optimization approach for the task allocation problem in embedded multi-core systems. The information therefore is obtained from a system description in AUTOSAR and runtime measurements of the runnables in hardware traces. Based on this an initial software partitioning of runnables to tasks is created. We then use a genetic algorithm to create and evaluate solutions to the task allocation problem. Each solution is hereby evaluated using a discrete event-based simulation, which allows the evaluation with regard to real-time properties, resource consumption and data-communication overhead. The significance of our approach is then shown in a case-study. There, we optimize the task allocation of an embedded system, whose complexity is comparable to that of an actual system, on a multi-core processor. Finally, the results of the optimization are transferred to an ECU Configuration Description to enable further development in compliance with the AUTOSAR methodology. KW - AUTOSAR KW - Multi-Objective Optimization KW - Multi-Core KW - Goodness-of-fit KW - Task Allocation Y1 - 2013 UR - https://ieeexplore.ieee.org/document/6636524 ER - TY - CHAP A1 - Braun, Jürgen A1 - Mottok, Jürgen A1 - Miedl, Christian A1 - Geyer, Dirk A1 - Minas, Mark T1 - Increasing the reliability of single and multicore systems with software rejuvenation and coded processing T2 - Automotive Safety & Security 2012, Sicherheit und Zuverlässigkeit für automobile Informationstechnik, 14.-15. Nov. 2012, Karlsruhe N2 - The safety of electric vehicles has the highest priority because it helps contribute to customer confidence and thereby ensures further growth of the electromobility market. Therefore in series production redundant hardware concepts like dual core microcontrollers running in lock-step-mode are used to reach ASIL D safety requirements given from the ISO 26262. Coded processing is capable of reducing redundancy in hardware by adding diverse redundancy in software, e.g. by specific coding of data and instructions. A system with two coded processing channels is considered. One channel is active and one is in cold standby. When the active channel fails, the service is switched from the active channel to the standby channel. It is imaginable that the two channels with implemented coded processing are running with time redundancy on a single core or on a multi core system where for example different ASIL levels are partitioned on different cores. In this paper a redundant concept based on coded processing and software rejuvenation will be taken into account. Y1 - 2012 UR - https://dl.gi.de/handle/20.500.12116/17555 SP - 163 EP - 178 ER - TY - CHAP A1 - Tomer, Amir A1 - Hagel, Georg A1 - Mottok, Jürgen A1 - Alt, Dorit A1 - Barak, Miriam I. A1 - Hadar, Irit T1 - CAPELLA: A conceptual framework for adaptive life-long learning T2 - IEEE Global Engineering Education Conference (EDUCON), 25-28 April 2017, Athens, Greece N2 - In this paper we describe a proposed framework for Cooperative Adaptive Personalized Education for Life-long Learning and Activation (CAPELLA). CAPELLA comprises four models: A Knowledge Organization Model, a Learning Process Model, a Community Collaboration Model and a Gaming Model. The underlying pedagogical approach is based on the four pillars of learning: Learning to know, learning to do, learning to collaborate and learning to be. Based on these models and principles, CAPELLA provides a theoretical framework that may assist IT developers to develop state-of-the-art educational platforms and advanced learning applications. Using an example of a UML Diagramming Workshop we demonstrate how CAPELLA incorporates the principles of Adaptive Learning. Y1 - 2017 U6 - https://doi.org/10.1109/EDUCON.2017.7943041 SP - 1463 EP - 1472 ER - TY - CHAP A1 - Schumm, Michael A1 - Joseph, Saskia A1 - Mottok, Jürgen A1 - Niemetz, Michael A1 - Schroll-Decker, Irmgard T1 - Lernarrangements im software engineering und deren evaluation – neue konzepte für hochschule und lebenslanges Lernen T2 - Tagungsband 5th Embedded Software Engineering Kongress, 3. bis 7. Dezember 2012, Sindelfingen Y1 - 2012 ER - TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen T1 - Simulationsbasierte Reliability-Analyse – Einflüsse von zufälligen Fehlern auf das Echtzeit-Scheduling T2 - Tagungsband 5th Embedded Software Engineering Kongress, 3. bis 7. Dezember 2012, Sindelfingen Y1 - 2012 SP - 613 EP - 622 ER - TY - CHAP A1 - Alfranseder, Martin A1 - Mottok, Jürgen T1 - Kommunikationsmechanismen für sicherheitskritische multi-core Echtzeit-Systeme T2 - 5th Automotive Summerschool, Regensburg, September 2012 Y1 - 2012 ER - TY - RPRT A1 - Pfaller, M. A1 - Mottok, Jürgen T1 - Developing the e-learning class ‘practical training in c’ Y1 - 2013 ER - TY - CHAP A1 - De, Sangita A1 - Niklas, Michael A1 - Rooney, Brian A1 - Mottok, Jürgen A1 - Brada, Premek T1 - Towards Translation of Semantics of Automotive Interface Description Models from Franca to AUTOSAR Frameworks BT - An Approach using Semantic Synergies T2 - 2019 International Conference on Applied Electronics (AE), 10-11 Sept. 2019, Pilsen, Czech Republic N2 - The automotive industry is eventually evolving into a complex network of services. The heterogeneous and distributed nature of automotive software systems demands flexible software components which can operate in different environments. Because of heterogeneous automotive development environments, the domain experts, must cope with too many diversities, adaption layers, and incompatibilities to design applications for the current generation of autonomous driving vehicles. In this context, interface adaptation is a promising approach to achieve flexibility without directly changing the respective components. AUTOSAR, which is the de-facto standard for describing automotive system architecture and is a hugely comprehensive standard allowing designers full control from abstract system description to bare metal level deployment. However, the vehicle subsystems have still evolved to include multifarious high-level domains not covered by AUTOSAR e.g. Infotainment, Telematics etc. Therefore, it seems beneficial to bridge the semantic gaps between AUTOSAR applications and other standards of automotive application domains. The goal of this paper is to investigate interface semantic mapping and achieve transparent integration of domain-specific applications using the translation of semantics among the AUTOSAR platform software component models and other software components models of open source development platforms e.g. GENIVI. A key goal of such a modelling approach is the reuse of existing interface description languages and respective code generators. This will enhance future interoperability and decrease in incompatibility among these platforms. KW - Adaptation models KW - ARXML KW - Automotive engineering KW - component model KW - Connectors KW - FRAMEWORK KW - Franca IDL KW - interface KW - Receivers KW - semantic KW - synergy KW - traits Y1 - 2019 U6 - https://doi.org/10.23919/AE.2019.8867018 SP - 1 EP - 6 PB - University of West Bohemia ER - TY - CHAP A1 - Rudolph, Alexander A1 - Voget, Stefan A1 - Mottok, Jürgen T1 - A consistent safety case argumentation for artificial intelligence in safety related automotive systems – An Evaluation of a New Conceptual Functional Safety Approach T2 - Embedded Real-Time Software and Systems Conference (ERST²), Jan 2018, Toulouse/France N2 - Regarding the actual automotive safety norms the use of artificial intelligence (AI) in safety critical environments like autonomous driving is not possible. This paper introduces a new conceptual safety modelling approach and a safety argumentation to certify AI algorithms in a safety related context. Therefore, a model of an AI-system is presented first. Afterwards, methods and safety argumentation are applied to the model, whereas it is limited to a specific subset of AI-systems, i.e. off-board learning deterministic neural networks in this case. Other cases are left over for future research. The result is a consistent safety analysis approach that applies state of the art safety argumentations from other domains to the automotive domain. This will enforce the adaptation of the functional safety norm ISO26262 to enable general AI methods in safety critical systems in future. Y1 - 2018 UR - https://hal.archives-ouvertes.fr/hal-02156048 ER - TY - CHAP A1 - Mucha, Matthias A1 - Mottok, Jürgen A1 - Deubzer, Michael T1 - Probabilistic worst case response time estimation for multi-core real-time systems T2 - 2015 4th Mediterranean Conference on Embedded Computing (MECO), 14-18 June 2015, Budva, Montenegro N2 - Traditional methods rely on Static Timing Analysis techniques to compute the Worst Case Response Time for tasks in real-time systems. Multi-Core real-time systems are faced up with concurrent task executions, semaphore accesses, and task migrations where it may be difficult to obtain the worst case upper bound. A new three staged probabilistic estimation concept is presented. Worst Case Response Times are estimated for tasksets which consist of tasks with multiple time bases. The concept involves data generation with sample classification and sample size equalization, model fit and Worst Case Response Time estimation on the basis of extreme value distribution models. A Generalized Pareto Distribution model fit method which includes threshold detection and parameter estimation is also presented. Sample classification in combination with the new Generalized Pareto Distribution model fit method allows to estimate Worst Case Response Times with low pessimism ranges compared to estimation methods that uses the Generalized Pareto or the Gumbel max distribution without sample classification. Y1 - 2015 SP - 31 EP - 36 ER -