TY - CHAP A1 - Raab, Peter A1 - Racek, Stanislav A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Data Flow Analysis of Software Executed by Unreliable Hardware T2 - 16th Euromicro Conference on Digital System Design, Los Alamitos, CA, USA N2 - The data flow is a crucial part of software execution in recent applications. It depends on the concrete implementation of the realized algorithm and it influences the correctness of a result in case of hardware faults during the calculation. In logical circuits, like arithmetic operations in a processor system, arbitrary faults become a more tremendous aspect in future. With modern manufacturing processes, the probability of such faults will increase and the result of a software's data flow will be more vulnerable. This paper shows a principle evaluation method for the reliability of a software's data flow with arbitrary soft errors also with the concept of fault compensation. This evaluation is discussed by means of a simple example based on an addition. KW - data flow KW - error probability KW - fault compensation KW - reliability analysis KW - software-implemented-hardwarefault-tolerance (SIHFT) Y1 - 2013 U6 - https://doi.org/10.1109/DSD.2013.35 SP - 243 EP - 249 ER - TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen A1 - Racek, Stanislav T1 - Reliability analysis of real-time scheduling by means of stochastic simulation T2 - 2012 International Conference on Applied Electronics (AE 2012), Pilsen, Czech Republic, 5 - 7 September 2012 N2 - We present a simulation-based approach to reliability analysis combined with a schedulability analysis of software intensive embedded real-time systems. In such a system not only does the software execution have to be hardened against soft errors, e.g., by means of coded processing or diverse execution, but also the real-time requirements have still to be met in the presence of such error to guarantee a safe operation of the system. For that reason, the influence regarding the real-time characteristics of a given sporadic error with a certain error rate is analyzed by means of a Monte Carlo simulation. Different safety design patterns are introduced and compared. Furthermore, the impact on the schedulability of an embedded system is discussed. Y1 - 2012 SP - 151 EP - 156 ER - TY - CHAP A1 - Raab, Peter A1 - Racek, Stanislav A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Reliability of Task Execution during Safe Software Processing T2 - 15th Euromicro Conference on Digital System Design, Cesme, Turkey N2 - This paper presents the reliability evaluation of task execution during safe software processing. The standard method of duplication in a safety-critical application can also be applied for tasks in a software system. But in addition to this, there is also the possibility for coded task processing to increase the reliability and availability of software. The presented analysis covers the reliability analysis of a single, a duplicated and a coded task by the technique of continuous time Markov processes. Markov processes are often used for the reliability evaluation of safety-critical systems. We introduce a method to describe the execution time of tasks by means of enhanced Markov models and their solution by numerical methods. KW - reliability analysis KW - continuous-time Markov process KW - error probability KW - Erlang-distribution Y1 - 2012 U6 - https://doi.org/10.1109/DSD.2012.110 SP - 84 EP - 89 ER - TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen T1 - Simulationsbasierte Reliability-Analyse – Einflüsse von zufälligen Fehlern auf das Echtzeit-Scheduling T2 - Tagungsband 5th Embedded Software Engineering Kongress, 3. bis 7. Dezember 2012, Sindelfingen Y1 - 2012 SP - 613 EP - 622 ER - TY - JOUR A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Reliability of data processing and fault compensation in unreliable arithmetic processors, Microprocessors and Microsystems JF - Microprocessors and Microsystems N2 - In logical circuits, like arithmetic operations in a processor system, arbitrary faults become a more tremendous aspect in future. Modern manufacturing processes lead to less reliability and higher vulnerability of software execution to soft-errors. The correctness of certain results is important especially for safety–critical applications whose reliability depends on the fault-free execution of each single instruction and the dependencies between them. The more complex a software is the more unreliable the outcome is. But, there is a contrary effect. If the probability for multiple faults increases, there is also the chance that two faults compensate each other and the result is correct again. This paper presents the basic ideas for such a reliability evaluation of a software's data flow with arbitrary soft-errors and the effect of fault compensation. Further, this evaluation provides a possibility to compare different implementations of a data flow with respect to the reliability. This is shown by the comparison of two different error codes as alternatives for coded data processing. Y1 - 2016 U6 - https://doi.org/10.1016/j.micpro.2015.07.014 VL - 40 IS - Februar SP - 102 EP - 112 PB - Elsevier ER - TY - CHAP A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Racek, Stanislav T1 - Proportionate fair based multicore scheduling for fault tolerant multicore real-time systems T2 - International Conference on Electrical and Information Technologies (ICEIT), 25-27 March 2015, Marakesch, Morocco N2 - In this paper we present a scheduling approach for safety critical, fault tolerant, multicore real-time embedded systems. For this kind of systems, not only the correctness of a computed result but also the strict adherence to timing requirements of computation is essential to avoid any kind of damage. To react to unpredictable, arbitrary hardware faults suitable error detection mechanisms have to be applied. The caused error itself and the detection and correction have great impact on the system's timing behavior. To still keep the real-time requirements, the used scheduling algorithm has to ensure maximum flexibility to disturbances of the timing. The group of Proportionate Fair (Pfairness) multicore scheduling algorithms has been proven to create an optimal schedule in polynomial time. The contribution of this paper is a Pfair-based algorithm that uses tight coupling between the error detection mechanisms and the scheduler of the real-time operating system to establish a loop-back connection. KW - Multicore processing KW - Time factors KW - Safety KW - Schedules KW - Scheduling algorithms KW - Real-time systems Y1 - 2015 U6 - https://doi.org/10.1109/EITech.2015.7162952 SP - 88 EP - 93 ER - TY - CHAP A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Modifikation des Taskzustandsmodells des LLREF-Schedulers auf einem Dual-Core-Prozessor T2 - Proceedings of the 2nd Embedded Software Engineering Congress, 8. bis 10. Dezember 2009, Sindelfingen Y1 - 2009 SP - 628 EP - 636 ER - TY - CHAP A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Osek-basierende Implementierung des LLREF-Scheduling-Algorithmus für eine Dual-Core-Architektur T2 - 2. Landshuter Symposium Mikrosystemtechnik, Tagungsband, 24. une 25. Februar 2010, Hochschule Landshut Y1 - 2010 SP - 343 EP - 349 ER - TY - CHAP A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Cyclic codes and error detection during data processing in embedded software systems T2 - Proceedings of the 4rd Embedded Software Engineering Congress (ESE), 5.-9. Dezember 2011, Sindelfingen Y1 - 2011 SP - 577 EP - 590 ER - TY - JOUR A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Multi-Core Scheduling in Embedded Systemen, Teil 1 JF - Hanser Automotive Y1 - 2010 IS - 1-2 SP - 18 EP - 22 ER - TY - JOUR A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Multi-Core Scheduling in Embedded Systemen, Teil 2 JF - Hanser Automotive Y1 - 2010 IS - 3-4 SP - 23 EP - 25 ER - TY - JOUR A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Multi-Core Scheduling in Embedded Systemen, Teil 3 JF - Hanser Automotive Y1 - 2010 IS - 5-6 SP - 14 EP - 16 ER - TY - JOUR A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Vavricka, Vlastimil T1 - Isomorphism between Linear Codes and Arithmetic Codes for Safe Data Processing in Embedded Software Systems JF - Computing and Informatics (CAI) N2 - We present a transformation rule to convert linear codes into arithmetic codes. Linear codes are usually used for error detection and correction in broadcast and storage systems. In contrast, arithmetic codes are very suitable for protection of software processing in computer systems. This paper shows how to transform linear codes protecting the data stored in a computer system into arithmetic codes safeguarding the operations built on this data. Combination of the advantages of both coding mechanisms will increase the error detection capability in safety critical applications for embedded systems by detection and correction of arbitrary hardware faults. Y1 - 2014 UR - https://pdfs.semanticscholar.org/eb7c/f626eb4dcf33bb9c615d477099188eadc76b.pdf?_ga=2.23977850.1374482597.1614464499-73487869.1612391519 VL - 33 SP - 721 EP - 734 ER - TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen A1 - Racek, Stanislav T1 - Comparison of Enhanced Markov Models and Discrete Event Simulation – for evaluation of probabilistic Faults in safety-critical real-time task sets T2 - Proceedings of EUROMICRO DSD 2014 - 17th Euromicro Conference on Digital System Design N2 - In this paper we present simulation and model based approaches for evaluating and validating the temporal and safety relevant properties of software intensive safety-critical real-time embedded systems. A high level reliability model of a safe task execution is described by a continuous-time Markov process, enhanced by the modeling of execution times. It is shown that the behavior - regarding real-time and safety metrics - of this theoretical model can be transferred into an abstract system timing model, which then can be analyzed by a discrete event simulation approach. The verification of the discrete event simulation by Markov models offers the possibility of a holistic approach for reliability analysis combined with schedulability analysis of complex safety-critical multicore real-time systems by the discrete event simulation. KW - Model KW - Stochastic simulation KW - reliability analysis KW - safe software processing KW - real-time operating system KW - multicore scheduling KW - discrete event simulation KW - fault injection Y1 - 2014 U6 - https://doi.org/10.1109/DSD.2014.42 SP - 591 EP - 598 ER - TY - CHAP A1 - Krämer, Stefan A1 - Simsek, Erol A1 - Braun, Jürgen A1 - Deubzer, Michael A1 - Stingl, Armin A1 - Hobelsberger, Martin A1 - Mottok, Jürgen T1 - Mut zu Fehlern, um die Qualität zu steigern – Fault-Injection zur Steigerung der Zuverlässigkeit T2 - Tagungsband, 6th Embedded Software Engineering, Kongress 2013, 2. bis 6. Dezember 2013, Sindelfingen Y1 - 2013 SN - 978-3-8343-2408-5 SP - 577 EP - 585 ER - TY - CHAP A1 - Seidl, M. A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Improving the reliability of an embedded real-time system by applying coded processing T2 - 4th Applied Research Conference, 5th July 2014, Ingolstadt Y1 - 2014 SN - 978-3-8440-2875-1 SP - 70 EP - 74 PB - Shaker CY - Aachen ER -