TY - CHAP A1 - Schubert, Martin J. W. A1 - Blödel, J. A1 - Conradi, P. A1 - Lafosse, P. A1 - Nebel, W. A1 - Neusser, S. A1 - Ryba, M. A1 - Schröder, D. T1 - Extending EDIF for Technology Data T2 - EDIF World Conference, 1989, San Jose, CA, USA, 11.-14. September Y1 - 1989 ER - TY - CHAP A1 - Ooi, Boon Yaik A1 - Lee, Wai-Kong A1 - Schubert, Martin J. W. A1 - Ooi, Yu-Wei A1 - Chin, Chee-Yang A1 - Woo, Wing-Hon T1 - A Flexible and Reliable Internet-of-Things Solution for Real-Time Production Tracking T2 - IEEE Industrial Electronics and Applications Conference (IEACon): 22.11.2021 - 23.11.2021, Penang, Malaysia N2 - The concept of Industrial Revolution 4.0 (IR4.0) has sparked the urgency of many manufacturers to revisit their manufacturing processes and search for opportunities to further improved their production output. Unfortunately, it is difficult to improve a process with inadequate data. Many of the SMEs in developing countries are still using manufacturing machines from the yesteryears which do not have computational and connectivity capabilities. Therefore, we developed an end-to-end Internet-of-Things (IoT) solution, which reliably tracks the production performance of manufacturing machines. This paper elaborates on the designs and the rationale behind it. As of the writing of this paper, our IoT system has been deployed in real manufacturing environment and has been running for approximately 90 days on a 24/7 basis without data lost. KW - industry 4.0 KW - IoT KW - production tracking KW - Smart Manufacturing Y1 - 2021 SN - 978-1-7281-9253-6 U6 - https://doi.org/10.1109/IEACon51066.2021.9654672 SP - 270 EP - 275 PB - IEEE ER - TY - CHAP A1 - Declerq, Michel A1 - Clément, F. A1 - Schubert, Martin J. W. A1 - Harb, Adnan A1 - Dutoit, Michel T1 - Design and Optimization of High-Voltage CMOS Devices Compatible wih a Standard 5V CMOS Technology T2 - Proceedings of IEEE Custom Integrated Circuits Conference, May 9-12 1993, San Diego, CA, USA N2 - High-voltage n- and p-MOSFETs fully compatible with a standard 5 V CMOS technology have been designed, optimized, and fabricated. No process changes are required. By modifying the logical equations generating one of the physical masks from the design masks, a p-type buffer region for the high-voltage p-MOS was easily implemented. This modification does not affect the low-voltage part of the circuits. These high-voltage devices have been used successfully as output drivers in semicustom arrays, and as building blocks for custom low- to high-voltage output interfaces. Aspects of reliability, device protection, and circuit design techniques are addressed. Y1 - 1993 SN - 0-7803-0826-3 U6 - https://doi.org/10.1109/CICC.1993.590766 SP - 24.6.1 EP - 24.6.4 ER - TY - CHAP A1 - Schubert, Martin J. W. A1 - Höfflinger, Bernd A1 - Zingg, René P. T1 - A New Analytical Charge Model for the Dual-Gate-Controlled Thin-Film SOI MOSFET T2 - Superlattices and Microstructures N2 - An analytical model for dual-gate-controlled SOI MOSFETs is presented, assuming uniformly doped p-silicon films. It is restricted to electron inversion layers and depletion regions, neglecting hole densities. It allows to account for the spatial description of electronic quantities in the silicon film. Due to the non-linearities of the semiconductor equations the model parameters must be extracted iteratively. Some applications are presented to demonstrate the usefulness of the model. Y1 - 1990 U6 - https://doi.org/10.1016/0749-6036(90)90218-V VL - 7 IS - 4 SP - 323 EP - 326 PB - Elsevier ER - TY - CHAP A1 - Schubert, Martin J. W. T1 - Mixed-Signal Event-Driven Simulation of a Phase-Locked Loop T2 - IEEE/VIUF International Workshops on Behavioral Modeling and Simulation (BMAS'99), October 4-6 1999, Orlando, Florida, USA N2 - The mixed-signal event-driven (MixED) simulationalgorithm using standard VHDL is capable of modelinga number of analog and mixed-signal problems in digital circuits, e.g. RCL networks representing pads or wires, charge pumps, dynamic logic, voltage-controlledoscillators, phase-locked loops, etc. Important featuresare single-kernel simulation as well as rapid A/D andD/A interfacing. This paper demonstrates the simulation of a phase-locked loop (PLL), which is one of the most interesting applications of the MixED method. Many digital designs contain a PLL as only mixed-signal building block. The MixED method allows to simulate such designs with standard VHDL. KW - mixed-signal event-drivensimulation KW - standard VHDL KW - analog models KW - PLL Y1 - 1999 UR - https://hps.hs-regensburg.de/~scm39115/homepage/research/mixed/mixed_publications/1999_bmas_pll.pdf ER - TY - CHAP A1 - Declerq, Michel A1 - Schubert, Martin J. W. A1 - Clément, F. T1 - 5V-to-75V CMOS Output Interfaces T2 - Proceedings of the1993 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 24-26 1993, San Francisco, CA, USA N2 - A family of CMOS low- to high-voltage output interface circuits based on a standard, unmodified low-voltage CMOS technology is described. Using only thin-oxide high-voltage (HV) devices with reduced V/sub GS/ (gate-to-source voltage) swing, it makes use of level-shift techniques to meet the constraints on the gate control signals. These static circuits permit the full output voltage swing of V/sub DDH/, while keeping the V/sub GS/ swing of the output devices within the safety limits, including during HV supply transients. Using a standard 2- mu m n-well CMOS technology, reliable, reproducible V/sub DS/ breakdown voltages as high as 120 V and 80 V have been obtained for HV-nMOS and HV-pMOS devices, respectively.< > Y1 - 1993 U6 - https://doi.org/10.1109/ISSCC.1993.280014 SP - 162 EP - 163 ER - TY - CHAP A1 - Schubert, Martin J. W. T1 - Operational Amplifier Modeling Using Event-Driven VHDL T2 - IEEE/VIUF International Workshops on Behavioral Modeling and Simulation (BMAS'97), October 20/21 1997, Washington D.C., USA N2 - A method to model high-gain feedback-loop analog amplifiers on an event driven timeaxis is presented. The demonstrator is coded in digital VHDL’93. In the event-driven scheme any node in the network must converge „on its own“ based on the information delivered from its neighbors, as no overall matrix is set up. For this reason signalloops with a loop gain larger than one are typically unstable. This communication presents a numerically stable generic model for high gain amplifiers with a userdefined feedback network. Non-ideal effects like offset or finite gain can be taken into account. Y1 - 1997 UR - https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.495.5356&rep=rep1&type=pdf ER - TY - CHAP A1 - Bartsch, Ernst A1 - Schubert, Martin J. W. T1 - Mixed Analog-Digital Circuit Modeling Using Event-Driven VHDL T2 - IEEE/VIUF International Workshops on Behavioral Modeling and Simulation (BMAS'97), Ocotober 20/21 1997, Washington D.C., USA N2 - The mixed-signal event-driven (MixED) method developed to simulate small portions of analog circuitry within a digital environment is demonstrated in a mixed signal application. The MixED models using concurrent iteration to account for analog nodes were coded and run in standard VHDL’93. Networks containing linear components such as sources, resistors, capacitors, inductors and operational amplifiers are presented. The possibility to manipulate resistors during runtime is used to simulate switches. Y1 - 1997 UR - https://hps.oth-regensburg.de/scm39115/homepage/research/mixed/mixed_publications/1997_bmas_circuit.pdf ER - TY - CHAP A1 - Schubert, Martin J. W. T1 - Mixed Analog-Digital Signal Modeling Using Event-Driven VHDL T2 - X Brazilian Symposium on Integrated Circuit Design (SBCCI'97), August 25-27 1997, Porto Alegre, Brazil N2 - A method for solving networks containing generic analog components such as resistors, capacitors and inductors onan event driven time axis using digital VHDL is presented. The components are modeled as complex state machines communicating with their neighbors using INOUT type ports. The method takes advantage of simulation deltas to iterate without simulation-time consumption. A limited range of implicit equations can be solved this way. Y1 - 1997 UR - http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=50F6F0DA594FB90976CC1474581BC139?doi=10.1.1.508.3657&rep=rep1&type=pdf SP - 77 EP - 86 ER - TY - CHAP A1 - Schubert, Martin J. W. T1 - Mixed Signal Modeling in VHDL by Distributed Local Iteration T2 - VHDL Form, Toledo, Spain, April 20-24, 1997 Y1 - 1997 ER - TY - CHAP A1 - Schubert, Martin J. W. A1 - Seign, Stefan A1 - Dai, Q. A1 - Hinterseer, Sebastian A1 - Pielmeier, F. A1 - Pietsch, Alexander A1 - Seebauer, C. A1 - Weiß, Josef A1 - Yu, C. A1 - Zenger, Stefan T1 - Capacitive Sensor Technology for Soil Moisture Monitoring Networks T2 - 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 5-8 Dec. 2017, Batumi, Georgia N2 - A sensor technology for tracking soil-moisture in agricultural fields is presented. A linear measurement method was developed to satisfy the need for cheap sensors with wide range of capacitance change such as factor 30. A combined wired and wireless network transmits data to a server. Various battery aspects are compared with respect to use in agriculture. Y1 - 2017 U6 - https://doi.org/10.1109/ICECS.2017.8292018 SP - 190 EP - 193 ER - TY - CHAP A1 - Schubert, Martin J. W. T1 - System Contemplations for Precision Irrigation in Agriculture T2 - AIP Conference Proceedings N2 - This communication contemplates political, biological and technical aspects for efficient and profitable irrigation in sustainable agriculture. A standard for irrigation components is proposed. The need for many, and three-dimensionally distributed, soil measurement points is explained, thus enabling the control of humidity in selected layers of earth. Combined wireless and wired data transmission is proposed. Energy harvesting and storage together with mechanical sensor construction are discussed. Y1 - 2017 SN - 9780735414969 U6 - https://doi.org/10.1063/1.4979393 VL - 1828 IS - 1 ER - TY - CHAP A1 - Schubert, Martin J. W. T1 - VHDL Based Simulation of a Delta-Sigma A/D Converter Clocked with a Phase-Locked Loop T2 - Design, Automation and Test in Europe, DATE'2001 Conference, March 13-16 2001, Munich N2 - The VHDL based mixed-signal event-driven (MixED) simulation method is employed to simulate a comprehensive system containing a number of mixed-signal building blocks: an analog waveform generator, a phase-locked loop and two ∆Σ modulators for A/D conversion. Y1 - 2001 UR - https://hps.hs-regensburg.de/~scm39115/homepage/research/mixed/mixed_publications/2001_date_pll_sigmadelta.pdf ER - TY - CHAP A1 - Schubert, Martin J. W. T1 - VHDL Based Simulation of a Sigma-Delta A/D Converter T2 - EEE/ACM International Workshop on Behavioral Modeling and Simulation (BMAS2000), October 19-20 2000, Orlando, Florida, USA, prodeedings N2 - The VHDL based mixed-signal event-driven (MixED) simulation method is employed to simulate a sigma-delta modulator for A/D conversion. Results are verified by experimental data and comparison to PSpice-AD simulations. Y1 - 2000 U6 - https://doi.org/10.1109/BMAS.2000.888367 ER - TY - CHAP A1 - Lee, Wai-Kong A1 - Schubert, Martin J. W. A1 - Ho, Stanley Jian-Qin T1 - Multi-source energy harvesting and storage for floating wireless-sensor-network nodes T2 - 2016 IEEE Industrial Electronics and Applications Conference (IEACon 2016), 20.-22. Nov. 2016, Kota Kinabalu, Malaysia Y1 - 2016 SN - 9781509009268 ER - TY - CHAP A1 - Schubert, Martin J. W. A1 - Lee, Wai-Kong A1 - Ooi, Boon Yaik T1 - Quantization and Sampling Effects in Fast Digitally Controlled Switch-Mode DC/DC Buck Converters T2 - 2021 IEEE Industrial Electronics and Applications Conference (IEACon): 22.11.2021 - 23.11.2021, Penang, Malaysia N2 - Software-defined control of DC/DC switch mode power converters features unequaled flexibility compared to analog control. For fast switching converters as recently used for low power applications, digital control may cause steady-state oscillations known as limit cycles. This effect based on a quantized duty cycle is compared to other aberrations such as output ripple voltage, which is inherent to any pulse-width modulator. A distinction is made between DC and AC errors. The latter are divided into synchronous and asynchronous output voltage disturbances. Synchronous AC errors are composed of the switching frequency and its harmonics. KW - aberrations due to digitization KW - digital pulse-width modulation (DPWM) KW - low power DC/DC buck conversion KW - output voltage sampling Y1 - 2021 SN - 978-1-7281-9253-6 U6 - https://doi.org/10.1109/IEACon51066.2021.9654272 SP - 56 EP - 61 PB - IEEE ER -