TY - CHAP A1 - Seebauer, Stefan A1 - Jahn, Sabrina A1 - Mottok, Jürgen T1 - Escape Rooms for teaching IT-Security T2 - 12th International Conference of Education, Research and Innovation (ICERI2019), 11-13 November 2019, Seville, Spain Y1 - 2019 U6 - https://doi.org/10.21125/iceri.2019.1623 SP - 6815 EP - 6824 ER - TY - CHAP A1 - Osinski, Lukas A1 - Mottok, Jürgen T1 - Control Flow Errors: A Discussion of Different Injection Strategies T2 - 32nd International Conference on Architecture of Computing Systems, ARCS Workshop 2019, 20-21 May 2019, Copenhagen, Denmark N2 - Among the available dependability assessment techniques, fault injection (FI) is widely adopted and strongly recommended by safety standards for the validation that functional and technical safety mechanisms are implemented correctly and effectively. The main challenge in fault injection assessments is the increasing complexity of system-on-chips as well as the increasing size of memory, which leads to enormous efforts to test every possible fault introduced to the system. Therefore, a number of publicly available fault injection frameworks utilize fault space pruning techniques to reduce the overall fault space and consequently the overall experiment duration. Most of the fault space pruning techniques mainly discuss the reduction of the number of data errors which have to be injected into registers and memory locations. However, control flow errors represent a further domain of possible errors on the application level. Usually for the evaluation of effectiveness of fault tolerance mechanisms against data errors, a single fault assumption at microarchitectural level (e.g. bit-flips) is assumed. In most cases, this assumption is equivalently applied to the program counter to investigate possible control flow errors. Due to this approach, the error space is consciously or unconsciously reduced to the possible erroneous jump targets that can be reached by a specific set of bit-flips in the program counter at a specified time during the program execution. This approach is considered valid regarding the corresponding fault assumption, but leads to negative effects on the significance of the injection and the resulting effectiveness of the tested fault tolerance mechanism. In this paper, we discuss different strategies for the analysis and injection of control flow errors and the resulting differences by considering the single fault assumption at microarchitectural and application level. Y1 - 2019 UR - http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8836207&isnumber=8836190 SP - 1 EP - 7 ER - TY - CHAP A1 - Lalo, Erjola A1 - Weber, Raphael A1 - Sailer, Andreas A1 - Mottok, Jürgen A1 - Siemers, Christian T1 - On Solving Task Allocation and Schedule Generation for Time-Triggered LET Systems using Constraint Programming T2 - 32nd International Conference on Architecture of Computing Systems, ARCS Workshop 2019, 20-21 May 2019, Copenhagen, Denmark N2 - The amount of safety-critical embedded systems in automotive development is heavily growing. Ensuring their reliability not only increases the complexity of functions but also requires determinism at design and execution time, which is considerably challenging to fulfill and verify for multi-core processors. The Logical Execution Time (LET) is recently recognized in automotive industry as an approach for ensuring deterministic functional behavior. However, to decrease the manual design effort and time for deploying such complex systems to multi-core platforms and for ensuring their strict timing and safety requirements, automatic solutions are needed. This work presents a solution for allocating tasks to multi-core processors and generating a time-triggered schedule for embedded systems considering safety, timing, and LET semantics. The approach we propose solves both challenges by defining them as a Constraint Satisfaction Problem (CSP). To examine our CSP formulation, we use MiniZinc, which is a solver-independent constraint modeling language that can employ a variety of solvers. In a case study, we explore optimizations of an industrial system that are enabled by scheduling and task allocation design decisions. Further, the performance of the proposed solutions is evaluated based on large set of synthetically generated system models. Y1 - 2019 UR - https://ieeexplore.ieee.org/abstract/document/8836201 SP - 1 EP - 8 ER - TY - CHAP A1 - Nagengast, Christian A1 - Osinski, Lukas A1 - Mottok, Jürgen T1 - Synchronization Techniques for Parallel Redundant Execution of Applications T2 - 32nd International Conference on Architecture of Computing Systems, ARCS Workshop 2019, 20-21 May 2019, Copenhagen, Denmark N2 - In fault tolerant systems, applications are replicated and executed to enable error detection and recovery. If one replica application fails, another is able to take its place and provide the correct results. This concept can benefit from parallel execution on separate execution units. The rise of multicore platforms supports the development of parallel software, by providing the adequate hardware. However, this raises challenges regarding the synchronization of the redundant strings of execution. Replica determinism means that given the same input, identical programs provide the same output. To ensure replica determinism, requirements regarding the synchronization can be split in two domains: data and time. This paper examines the state of the art of synchronization techniques for parallel replicated execution in the context of fault tolerant systems. We analyze the requirements regarding synchronization within the time and data domain and compare different concepts of hardware (multicore, multiprocessor and multi-PCB) and software (processes, threads). Y1 - 2019 UR - http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8836209&isnumber=8836190 SP - 1 EP - 8 PB - IEEE ER - TY - CHAP A1 - Mottok, Jürgen A1 - Reichenberger, Marcus T1 - Use of Static Analysis and Coding Guidelines in embedded Systems Software T2 - 1st Applied Research Conference, ARC 2019, 8 July 2019, Regensburg Y1 - 2019 SN - 978-3-96409-182-6 SP - 571 EP - 578 PB - Pro BUSINESS ER - TY - CHAP A1 - Schmid, Michael A1 - Mottok, Jürgen ED - Schoeberl, Martin ED - Hochberger, Christian ED - Uhrig, Sascha ED - Brehm, Jürgen ED - Pionteck, Thilo T1 - Asynchronous Critical Sections in Real-Time Multiprocessor Systems T2 - Architecture of Computing Systems - ARCS 2019, 32nd International Conference, Copenhagen, Denmark, May 20-23, 2019, Proceedings N2 - Sharing data across multiple tasks in multiprocessor systems has intensively been studied in the past decades. Various synchronization protocols, the most well-known being the Priority Inheritance Protocol or the Priority Ceiling Protocol, have been established and analyzed so that blocking times of tasks waiting to access a shared resource can be upper bounded. To the best of our knowledge, all of these protocols share one commonality: Tasks that want to enter a critical section, that is already being executed by another task, immediately get blocked. In this paper, we introduce the Asynchronous Priority Ceiling Protocol (A-PCP), which makes use of aperiodic servers to execute the critical sections asynchronously, while the calling task can continue its work on non-critical section code. For this protocol, we provide a worst-case response time analysis of the asynchronous computations, as well as necessary and sufficient conditions for a feasibility analysis of a set of periodic tasks using the proposed synchronization model on a system that preemptively schedules the tasks under the rate-monotonic priority assignment. Y1 - 2019 U6 - https://doi.org/10.1007/978-3-030-18656-2_5 SP - 56 EP - 67 PB - Springer CY - Cham ER - TY - CHAP A1 - Renner, Sebastian A1 - Pozzobon, Enrico A1 - Mottok, Jürgen A1 - Hackenberg, Rudolf T1 - Benchmarking Software Implementations of 1st Round Candidates of the NIST LWC Project on Microcontrollers T2 - 3rd Lightweight Cryptography Workshop at NIST, Gaithersburg, USA N2 - This paper introduces a custom framework for benchmarking software implementations from the National Institute of Standards and Technology (NIST) Lightweight Cryptography (LWC) project on embedded devices. We present the design and core functions of the framework and apply it to various NIST LWC authenticated encryption with associated data (AEAD) ciphers. Altogether, we evaluate the speed of 213 submitted algorithm vari-ants on four different microcontroller units (MCUs), including 32 bit ARM and 8 bit AVR architectures. To allow a more meaningful comparison, we also conduct code size tests on all four boards and RAM utilization tests on one test platform. Y1 - 2019 UR - https://csrc.nist.gov/CSRC/media/Events/lightweight-cryptography-workshop-2019/documents/papers/benchmarking-software-implementations-lwc2019.pdf ER - TY - CHAP A1 - Renner, Sebastian A1 - Mottok, Jürgen ED - Trinitis, Carsten ED - Pionteck, Thilo T1 - Towards Key Management Challenges in the Smart Grid T2 - ARCS Workshop 2019 - 32nd International Conference on Architecture of Computing Systems, 20-21 May 2019, Copenhagen, Denmark N2 - The used technology in the power system is subject of great change. Through the use of smart devices, the systems in the power grid get interconnected between each other and remote networks. Especially the remote access to the critical smart grid environment involves new challenges in the area of security. To ensure the transmitted data and the access to the system is secured, cryptographic mechanisms have to be implemented. One critical part in this task is the management of cryptographic keys. This paper explains and defines a set of basic requirements for cryptographic key management in the smart grid. These requirements are derived from challenges present in common corporate environments. Then, basic approaches in the field of key management are stated and evaluated for the applicability in the power system. Different protocols for the implementation of key management strategies are shown and an assessment regarding their suitability for the defined requirements is conducted. KW - Cryptographic key management KW - smart grid security KW - post-quantum cryptography Y1 - 2019 UR - https://ieeexplore.ieee.org/document/8836205 SN - 978-3-8007-4957-7 PB - VDE-Verlag CY - Berlin ER - TY - CHAP A1 - De, Sangita A1 - Niklas, Michael A1 - Mottok, Jürgen A1 - Brada, Přemek T1 - A Semantic Analysis of Interface Description Models of Heterogeneous Vehicle Application Frameworks: An Approach Towards Synergy Exploration T2 - MODELSWARD 2019: Proceedings of the 7th International Conference on Model-Driven Engineering and Software Development, 20.02.2019 - 22.02.2019, Prague, Czech Republic N2 - As the world is getting more connected, the demands of services in automotive industry are increasing with the requirements such as IoT (Internet of Things) in cars, automated driving, etc. Eventually, the automotive industry has evolved to a complex network of servi ces, where each organization depends on the other organizations, to satisfy its service requirements in different phases of the vehicle life cycle. Because of these heterogeneous and complex development environments, most of the vehicle component interface models need to be specified in various manifest ations to satisfy the semantic and syntactic requirements, specific to different application development environments or frameworks. This paperdescribes an approach to semantic analysis of components interfaces description models of heterogeneous frameworks, that are used for vehicle applications. The proposed approach intends to ensure that interface description models of different service-based vehicle frameworks can be compared, correlated and re-used based on semantic synergies, across different vehicle platforms, development environments and organizations. The approach to semantic synergy exploration could further provide the knowledge base for the increase in interoperability, overall efficiency and development of an automotive domain specific general software solutions, by facilitating coexistence of components of heterogeneous frameworks in the same high-performance ECU for future vehicle software. KW - Application: Framework KW - IDL KW - Semantic: Mapping Y1 - 2019 SN - 978-989-758-358-2 SP - 394 EP - 401 PB - SCITEPRESS ER - TY - CHAP A1 - De, Sangita A1 - Mottok, Jürgen A1 - Niklas, Michael A1 - Brada, Premek ED - Trinitis, Carsten ED - Pionteck, Thilo T1 - Semantic Synergy Exploration in Interface Description Models of Heterogeneous Vehicle Frameworks: Towards Automotive Meta Interface Description Model T2 - ARCS 2019: 32nd GI/ITG International Conference on Architecture of Computing Systems May 20 - 21, 2019, Technical University of Denmark, Copenhagen, Denmark Workshop, Proceedings N2 - This The vehicle is evolving to a complex network of heterogeneous subsystems of ECUs, sensors and actuators, each with different computational requirements. These sub-systems are connected via bus systems following different communication paradigms like e.g. signal based or service-oriented communications. This has led to the heterogeneous syntax of describing interfaces even though the semantics of the interfaces are similar. The wide variety of Interface Description Languages (IDLs) in automotive industry hinders partly with the efficient collaboration between different suppliers and the OEMs in the automotive industry. Given this wide variety of automotive IDLs, what could be more beneficial, from a software engineering point of view, is a generic automotive domain specific IDL that can satisfy all the fundamental requirements of the heterogeneous subsystems. This paper describes an approach to compare and correlate IDLs based on semantic similarities of the languages, considering the two aspects: application description and underlying message frameworks used in the different domains of given automotive subsystems. With the exploration of semantic synergies between the IDLs, various domain specific and domain-agnostic frameworks can be compared and correlated. The results can be generalized and abstracted to define a generic Meta IDL which could support use cases like e.g. domain-agnostic functional models and migration of software components between different kinds of automotive subsystems. Y1 - 2019 UR - https://ieeexplore.ieee.org/document/8836199 SN - 978-3-8007-4957-7 SP - 63 EP - 70 PB - VDE VERLAG CY - Berlin ER - TY - CHAP A1 - Thomeczek, Ludwig A1 - Attenberger, Andreas A1 - Kolb, Johannes A1 - Matoušek, Vaclav A1 - Mottok, Jürgen ED - Trinitis, Carsten ED - Pionteck, Thilo T1 - Measuring Safety Critical Latency Sources using Linux Kernel eBPF Tracing T2 - ARCS 2019: 32nd International Conference on Architecture of Computing Systems : workshop proceedings, May 20- 21, 2019, Technical University of Denmark, Copenhagen, Denmark Y1 - 2019 UR - https://ieeexplore.ieee.org/abstract/document/8836200 SN - 978-3-8007-4957-7 PB - VDE VERLAG GMBH CY - Berlin ER -