TY - CHAP A1 - Lalo, Erjola A1 - Deubzer, Michael A1 - Schmidhuber, Stefan A1 - Oklapi, Erna A1 - Mottok, Jürgen T1 - Task Priority Optimization in Real-Time Multi-Core Embedded Systems T2 - 4. Landshuter Symposium Mikrosystemtechnik, Mikrosystemtechnik als Schlüsseltechnologie der Systemintegration, Tagungsband zum Symposium 12./13. März 2014, Hochschule Landshut N2 - The shift from single-core to multi-core processors in real-time embedded systems leads to communication based effects on timing such as inter-core communication delays and blocking times. Moreover, the complexity of the scheduling problem increases when multi-core processors are used. In priority-based-scheduling, a fixed priority assignment is used in order to enable predictable behavior of the system. Predictability means that the system has to be analyzable which allows the detection of problems coming from scheduling decisions. For fixed priority scheduling in multi-core real-time embedded systems, a proper task priority assignment has to be done in a way that the system has minimal effects on timing. In this paper, we present an approach for finding near-optimal solutions for task priority assignment and the preemption/cooperation problem. A genetic algorithm is hereby used to create priority assignment solutions. A timing simulator is used for evaluation of each solution regarding real-time properties, memory consumption and communication overhead. In a case study we demonstrate that the proposed approach performs better than well known and single-core optimal heuristics for relatively complex systems. Y1 - 2014 SN - 978-3-9812696-5-9 SP - 96 EP - 109 CY - Landshut ER - TY - CHAP A1 - Alfranseder, Martin A1 - Deubzer, Michael A1 - Justus, Benjamin A1 - Mottok, Jürgen A1 - Siemers, Christian T1 - An Efficient Spin-Lock Based Multi-Core Resource Sharing Protocol T2 - 33rd IEEE International Performance, Computing, and Communications Conference (IPCCC), Austin (TX), USA, 5-7 December 2014 N2 - We present in this paper a new lock-based resource sharing protocol PWLP (Preemptable Waiting Locking Protocol) for embedded multi-core processors. It is based on the busy-wait model and works with non-preemptive critical sections while task may be preempted by tasks with a higher priority when waiting for resources. Our protocol can be applied in partitioned as well as global scheduling scenarios, in which task-fix, job-fix or dynamically assigned priorities may be used. Furthermore, the PWLP permits nested requests to shared resources. Finally, we present a case study based on event-based simulations in which the FMLP (Flexible Multiprocessor Locking Protocol) and the proposed PWLP are compared. Y1 - 2014 U6 - https://doi.org/10.1109/PCCC.2014.7017090 ER - TY - CHAP A1 - Helm, C. A1 - Deubzer, Michael A1 - Mottok, Jürgen ED - Ivanov, Artem ED - Bicker, Marc ED - Patzelt, Peter T1 - Analyse der Echtzeiteigenschaften von Multicore Speicherarchitekturen in Eingebetteten Systemen mittels einer konfigurierbaren Simulationssoftware T2 - 4. Landshuter Symposium Mikrosystemtechnik : Mikrosystemtechnik als Schlüsseltechnologie der Systemintegration, Tagungsband zum Symposium 12./13. März 2014, Hochschule Landshut Y1 - 2014 SN - 978-3-9812696-5-9 SP - 109 EP - 117 CY - Landshut ER - TY - CHAP A1 - Lalo, Erjola A1 - Schmidhuber, Stefan A1 - Deubzer, Michael A1 - Mottok, Jürgen T1 - Extended Task Priority and Preemptability Optimization in Real-Time Multi-Core Embedded Systems T2 - 4th Applied Research Conference, 5th July 2014, Ingolstadt Y1 - 2014 SN - 978-3-8440-2875-1 SP - 90 EP - 95 CY - Ingolstadt ER - TY - CHAP A1 - Mottok, Jürgen A1 - Krämer, Stefan A1 - Deubzer, Michael A1 - Hobelsberger, Martin A1 - Martin, Felix T1 - Hardware Based Tracing of Embedded Multi-Core Systems T2 - 4th Applied Research Conference, 5th July 2014, Ingolstadt Y1 - 2014 SN - 978-3-8440-2875-1 ER - TY - CHAP A1 - Sailer, Andreas A1 - Schmidhuber, Stefan A1 - Deubzer, Michael A1 - Alfranseder, Martin A1 - Mucha, Matthias A1 - Mottok, Jürgen T1 - Optimizing the task allocation step for multi-core processors within autosar T2 - 2013 International Conference on Applied Electronics, IEEE, Pilsen, Czech Republic N2 - We present a model-based optimization approach for the task allocation problem in embedded multi-core systems. The information therefore is obtained from a system description in AUTOSAR and runtime measurements of the runnables in hardware traces. Based on this an initial software partitioning of runnables to tasks is created. We then use a genetic algorithm to create and evaluate solutions to the task allocation problem. Each solution is hereby evaluated using a discrete event-based simulation, which allows the evaluation with regard to real-time properties, resource consumption and data-communication overhead. The significance of our approach is then shown in a case-study. There, we optimize the task allocation of an embedded system, whose complexity is comparable to that of an actual system, on a multi-core processor. Finally, the results of the optimization are transferred to an ECU Configuration Description to enable further development in compliance with the AUTOSAR methodology. KW - AUTOSAR KW - Multi-Objective Optimization KW - Multi-Core KW - Goodness-of-fit KW - Task Allocation Y1 - 2013 UR - https://ieeexplore.ieee.org/document/6636524 ER - TY - CHAP A1 - Sailer, Andreas A1 - Schmidhuber, Stefan A1 - Deubzer, Michael A1 - Mottok, Jürgen T1 - Amalthea – Plattform für kontinuierliche, modellbasierte Entwicklung T2 - Tagungsband, 6th Embedded Software Engineering, Kongress 2013, 2. bis 6. Dezember 2013, Sindelfingen Y1 - 2013 SP - 538 EP - 544 ER - TY - CHAP A1 - Mucha, Matthias A1 - Mottok, Jürgen A1 - Deubzer, Michael T1 - Probabilistic worst case response time estimation for multi-core real-time systems T2 - 2015 4th Mediterranean Conference on Embedded Computing (MECO), 14-18 June 2015, Budva, Montenegro N2 - Traditional methods rely on Static Timing Analysis techniques to compute the Worst Case Response Time for tasks in real-time systems. Multi-Core real-time systems are faced up with concurrent task executions, semaphore accesses, and task migrations where it may be difficult to obtain the worst case upper bound. A new three staged probabilistic estimation concept is presented. Worst Case Response Times are estimated for tasksets which consist of tasks with multiple time bases. The concept involves data generation with sample classification and sample size equalization, model fit and Worst Case Response Time estimation on the basis of extreme value distribution models. A Generalized Pareto Distribution model fit method which includes threshold detection and parameter estimation is also presented. Sample classification in combination with the new Generalized Pareto Distribution model fit method allows to estimate Worst Case Response Times with low pessimism ranges compared to estimation methods that uses the Generalized Pareto or the Gumbel max distribution without sample classification. Y1 - 2015 SP - 31 EP - 36 ER - TY - CHAP A1 - Sailer, Andreas A1 - Deubzer, Michael A1 - Lüttgen, Gerald A1 - Mottok, Jürgen T1 - CoreTAna: A Trace Analyzer for Reverse Engineering Real-Time Software T2 - IEEE 23rd International Conference on Software Analysis, Evolution, and Reengineering (SANER), March 14 to March 18 2016, Suita, Osaka, Japan N2 - With the availability of the AUTOSAR standard, model-driven methodologies are becoming established in theautomotive domain. However, the process of creating models ofexisting system components is often difficult and time consuming, especially when legacy code has to be re-used or informationabout the exact timing behavior is needed. In order to tackle thisreverse engineering problem, we present CoreTAna, a novel toolthat derives an AUTOSAR compliant model of a real-time systemfrom a dynamic analysis of its trace recordings. This paper givesan overview of CoreTAna's current features and discusses itsbenefits for reverse engineering. KW - AUTOSAR KW - tracing KW - profiling KW - timing model KW - reverse engineering Y1 - 2016 U6 - https://doi.org/10.1109/SANER.2016.36 ER - TY - JOUR A1 - Deubzer, Michael A1 - Mottok, Jürgen A1 - Bärwald, Andreas T1 - Dependability-Betrachtung von Multicore-Scheduling JF - HANSER Automotive N2 - Der Embedded Markt stellt sich auf eine neue Herausforderung ein: denUmstieg von Singlecore- auf Multicore-Prozessorsysteme. Dabei soll dieUmsetzung der Norm ISO 26262 die Funktionale Sicherheit der elektri-schen und elektronischen Systeme im Kraftfahrzeug gewährleisten. In diesem Beitrag betrachten die Hochschule Regensburg und die TÜV SüdAutomotive GmbH das Scheduling eines Echtzeitsystems als ein sicher-heitsrelevantes Sub-System. Y1 - 2010 UR - https://res.cloudinary.com/sternwald-systems/raw/upload/v1/hugoprd/ARTIKEL_ATTACH/00207DD4_0669BA3F5B24/4b2124fb030a4d3d5a42a83aaec4bddadebe3077/AM_2010_11_Dependability-Betrachtung-von-Multicore-Scheduling.pdf IS - 11 SP - 24 EP - 27 ER -