TY - CHAP A1 - Thomeczek, Ludwig A1 - Attenberger, Andreas A1 - Kolb, Johannes A1 - Matoušek, Vaclav A1 - Mottok, Jürgen ED - Trinitis, Carsten ED - Pionteck, Thilo T1 - Measuring Safety Critical Latency Sources using Linux Kernel eBPF Tracing T2 - ARCS 2019: 32nd International Conference on Architecture of Computing Systems : workshop proceedings, May 20- 21, 2019, Technical University of Denmark, Copenhagen, Denmark Y1 - 2019 UR - https://ieeexplore.ieee.org/abstract/document/8836200 SN - 978-3-8007-4957-7 PB - VDE VERLAG GMBH CY - Berlin ER - TY - JOUR A1 - Schmid, Michael A1 - Fritz, Florian A1 - Mottok, Jürgen T1 - Fine-Grained Parallel Applications in Real-Time Multiprocessor Systems JF - Journal of Systems Architecture N2 - Lately, parallel task models have received much attention in the development of real-time multiprocessor systems, as they allow highly compute-intensive tasks to have shorter deadlines which is very much required in modern reactive systems. However, missing modularity and portability can make parallel programming a cumbersome endeavor. As a consequence, compute-intensive sectors in the desktop and server segment have relied on parallelism frameworks such as Intel Threading Building Blocks, Cilk and OpenMP. These parallelism frameworks, however, are optimized for decent average case performance and consequently, do not meet the strict requirements imposed by real-time systems. In this paper, we present a proof-of-concept parallelism framework which was implemented in particular for soft real-time systems and having tight timing and safety requirements of such critical systems in mind. The proposed runtime system implements static memory allocation in a work-stealing environment that conforms to the strict space and tight probabilistic time bounds of work-stealing schedulers. Furthermore, we evaluate the performance of this framework by conducting multiprogrammed benchmarks on a real-time embedded multicore architecture. KW - Real-time KW - Work-stealing KW - Thread pool KW - Task model KW - Parallel programming Y1 - 2021 U6 - https://doi.org/10.1016/j.sysarc.2022.102393 VL - 124 PB - Elsevier ER - TY - JOUR A1 - Weiss, Nils A1 - Pozzobon, Enrico A1 - Mottok, Jürgen A1 - Matoušek, Václav T1 - Automated Reverse Engineering of CAN Protocols JF - Neural Network World N2 - Car manufacturers define proprietary protocols to be used inside their vehicular networks, which are kept an industrial secret, therefore impeding independent researchers from extracting information from these networks. This article describes a statistical and a neural network approach that allows reverse engineering proprietary controller area network (CAN)-protocols assuming they were designed using the data base CAN (DBC) file format. The proposed algorithms are tested with CAN traces taken from a real car. We show that our approaches can correctly reverse engineer CAN messages in an automated manner. Y1 - 2021 U6 - https://doi.org/10.14311/NNW.2021.31.015 SN - 1210-0552 VL - 31 IS - 4 SP - 279 EP - 295 ER - TY - JOUR A1 - De, Sangita A1 - Niklas, Michael A1 - Brian, Rooney A1 - Mottok, Jürgen A1 - Brada, Premek T1 - Semantic Mapping of Component Framework Interface Ontologies for Interoperability of Vehicle Applications JF - Procedia Computer Science N2 - Over the past few years, ontology merging, and ontology semantic alignment has gained significant interest as research topics in automotive application domain for finding solutions to semantic data heterogeneity. To accomplish the complex and novel vehicle service requirements such as autonomous driving, V2X (Vehicle-to-Vehicle communication), etc. the automotive applications involve collaborations of several platform-specific data from heterogeneous enterprises component frameworks and consequently there has been increase in data interoperability issues. At the application component level, data interoperability relies on the semantic alignment or mapping between the various component framework interfaces data models represented as XML schemas (XSD). With the XML schemas being the preferred standard for the interface description exchange between most of the automotive application domain components, however, the data interoperability between the semantically equivalent but structurally different data constructs of multiple heterogeneous XSDs stands as a challenge in the absence of an ontology-based approach. To confront this crucial requirement for data interoperability and to increase in effect the reuse of existing components through their interfaces, we propose an approach to semantically map the various component framework interface data models when expressed as ontology schemas, based on the exploration of semantic synergies. The transformation between XSD and RDF (Resource Description Framework) schema representations and the use of queries over the ontology schemas for semantic mapping are demonstrated including a real-world case study. KW - component KW - interface KW - mapping KW - ontology KW - semantic Y1 - 2020 U6 - https://doi.org/10.1016/j.procs.2020.03.151 VL - 170 IS - 2 SP - 813 EP - 818 PB - Elsevier ER - TY - CHAP A1 - Schmid, Michael A1 - Mottok, Jürgen ED - Queudet, Audrey T1 - Response Time Analysis of Parallel Real-Time DAG Tasks Scheduled by Thread Pools T2 - 29th International Conference on Real-Time Networks and Systems (RTNS 2021): 07.04. - 09 04 2021, Nantes, France N2 - Modern high-end embedded systems nowadays have to process enormous amounts of data. In order to speed up the computations and fully exploit the resources of the underlying hardware architectures, software developers can avail parallelism frameworks such as Intel Threading Building Blocks or compiler extensions as OpenMP. They ease the development of parallel applications by providing interfaces for common parallel design patterns and by internally distributing the work among the workers of a thread pool. However, such frameworks and compiler extensions do not yet support the stringent timing requirements of real-time systems and therefore, an adaption of their computation model to the sector of real-time systems needs to be conducted. In this paper, we address the problem of scheduling parallel real-time directed acyclic graphs tasks on multiprocessor architectures where the subtasks are dispatched among and executed by the workers of a thread pool. In contrast to existing work in the state-of-the-art, we limit the maximum parallelism of real-time tasks not by the number of processors in the system, but by the number of worker threads used in the thread pool of each real-time application. For this model, we derive a worst-case response time analysis for task sets scheduled by a preemptive global fixed-priority scheduler. In order to evaluate the performance of our response time analysis, we further perform schedulability tests on generated task sets and compare the results to existing feasibility analyses in the current state-of-the-art. KW - directed acyclic graph KW - parallel task KW - Real-time systems KW - real-time, scheduling KW - response time analysis KW - thread pool Y1 - 2021 SN - 9781450390019 U6 - https://doi.org/10.1145/3453417.3453419 SP - 173 EP - 183 PB - Association for Computing Machinery CY - New York ER - TY - JOUR A1 - Fuhrmann, Thomas A1 - Mottok, Jürgen T1 - Ethical, intercultural and professional impulses integrated into a transmission systems lecture JF - 2017 IEEE Global Engineering Education Conference (EDUCON), 25-28 April 2017, Athens, Greece N2 - In the sixth semester of the bachelor study course “Electrical Engineering and Information Technology”, a lecture “Transmission Systems” is given. It explains basic principles, circuits and systems of electrical and optical transmission systems. Short intellectual impulses, which address professional, intercultural and ethical issues of engineers' working life are integrated into this regular lecture. In each lecture unit, an impulse with one specific topic is given approximately in the middle of the lecture hour. An evaluation was done at the end of the semester, which shows that most of the students remember the discussed topics and state high interest due to high importance for their professional life. Due to these encouraging results, this concept will be developed further. KW - Engineering Education KW - Ethics Education KW - Electrical Engineering Y1 - 2017 U6 - https://doi.org/10.1109/EDUCON.2017.7942829 SP - 92 EP - 95 PB - IEEE ER - TY - CHAP A1 - Kopp, Felix A1 - Köhler, Thorsten A1 - Mottok, Jürgen ED - Ivanov, Artem ED - Bicker, Marc ED - Patzelt, Peter T1 - Bildgebende Verfahren zur dreidimensionalen Rekonstruktion aus Bildsequenzen basierend auf der Bundler SFM Toolchain T2 - 4. Landshuter Symposium Mikrosystemtechnik : Mikrosystemtechnik als Schlüsseltechnologie der Systemintegration, Tagungsband zum Symposium 12./13. März 2014, Hochschule Landshut N2 - Vorgestellt wird der Structure from Motion (SFM)Toolchain Bundler zur Erzeugung von Punktwolken aus unkalibrierten Kameraaufnahmen und deren Optimierungsmöglichkeiten durch zeitnahe Verfahren zur Interessenpunktextraktion. Das Extrahieren markanter Punkte aus Bildern beinhaltet eines der zeitintensivsten sowie herausforderndsten Aufgaben im dreidimensionalen Rekonstruktionsprozess. Vor allem im Hinblick auf die Integration von Structure from Motion Verfahren auf eingebettete Systeme sind Rechenzeit und Speicherverbrauch von hohem Interesse. Für dreidimensionale Rekonstruktionsalgorithmen ist das Finden akkurater Punktkorrespondenzen von hoher Priorität. Die Anforderungen an Punktdetektor, -deskriptor und -matcher sind dementsprechend hoch. Untersucht wurden die Ansätze zur Interessenpunktextraktion. Hierzu gehören, der von der Bundler SFM Toolchain genutzte, Scale-invariant feature transform (SIFT) sowie Speeded Up Robust Features (SURF), Binary Robust Invariant Scalable Keypoints (BRISK) und Fast Retina Keypoint (FREAK). Es wird gezeigt, dass das Ersetzen von SIFT in der Toolchain vor allem durch die binären Deskriptoren BRISK und FREAK zu wesentlich kürzeren Laufzeiten führen kann. Dies ist vor allem für eingebettete Systeme mit eingeschränkter Rechenleistung von Bedeutung. In Bezug auf die Genauigkeit der gefundenen Punktkorrespondenzen übertreffen sowohl FREAK als auch BRISK die nicht binären Ansätze im Anwendungsprofil. Zur Beschreibung von Interessenpunkten sind die binären Ansätze eine sinnvolle Optimierungsmöglichkeit hinsichtlich Laufzeit und Genauigkeit, während der in BRISK enthaltene Detektor nicht an die Performance der nicht binären Alternativen herankommt. Insgesamt betrachtet wurden die besten Ergebnisse (Laufzeit und Genauigkeit) mit den Kombinationen SURF/FREAK und SURF/BRISK erreicht. Die evaluierten Algorithmen(SIFT,SURF,BRISK,FREAK) sollen künftig in der Umgebung einer kompletten 3D-Rekonstruktions-Toolchain getestet und ausgewertet werden. Hierbei ist auch auf die Abhängigkeit von verschiedenen Matching-Verfahren zu achten. Darüber hinaus sollen weitere Optimierungsmöglichkeiten für Anwendungen basierend auf Bündelausgleichung untersucht werden. KW - Bildfolge KW - Bildgebungsverfahren KW - Bildrekonstruktion KW - Bündelung KW - dreidimensionale Struktur KW - Oberflächenrekonstruktion Y1 - 2014 SN - 978-3-9812696-5-9 SP - 118 EP - 125 CY - Landshut ER - TY - CHAP A1 - Bayer, Michael A1 - Noebauer, Josef A1 - Mottok, Jürgen T1 - Weiterentwicklung eines portablen OSEK-OS basierten Echtzeitbetriebssystems zu einem konfigurierbaren AUTOSAR-OS T2 - 4. Landshuter Symposium Mikrosystemtechnik, Mikrosystemtechnik als Schlüsseltechnologie der Systemintegration, Tagungsband zum Symposium 12./13. März 2014, Hochschule Landshut N2 - AUTOSAR spezifiziert ein statisches Echtzeitbetriebssystem (AUTOSAR-OS), welches auf die Bedürfnisse der Automobilindustrie zugeschnitten ist. Dabei stellt die AUTOSAR-OS-Spezifikation im Wesentlichen eine Weiterentwicklung von OSEK-OS dar. Die Unterschiede zu einem OSEK-OS sind im Wesentlichen eine erweiterte Programmierschnittstelle für Counter, Schedule Tables zur Abbildung komplexer zeitgesteuerter Abläufe und Stack Monitoring. Der Scheduler arbeitet prioritätsbasiert und unterstützt unterbrechbare und nicht unterbrechbare Tasks. Eine Ressourcenverwaltung mit Priority Ceiling Protokoll verhindert Deadlocks und Prioritäteninversion. Tasks sind entweder als "Basic Tasks" oder "Extended Tasks" konfiguriert. Nach einer kurzen Vorstellung der OS-Spezifikation wird eine darauf basierte Architektur für das Betriebssystem hergeleitet. Die konkrete Implementierung ist aufgeteilt in einen konfigurationsabhängigen Teil und einen statischen Quellcodeteil. Der konfigurationsabhängige Teil wird von einem Quellcodegenerator erzeugt. Der statische Teil wird in einer Schichtenarchitektur erstellt, um eine Trennung zwischen plattformabhängigem und plattformunabhängigem Quellcode zu erreichen, da die hierfür vorgesehene AUTOSAR-Methode nicht ausreicht. Die Portierung des OS auf eine neue Hardwareplattform zeigt, dass nur die plattormabhängige Quellcodeschicht des Betriebssystems geändert werden muss. Bei der Validierung des Betriebssystems wurde neben einem funktionellen Test auch die Performance für charakteristische Aufgaben, wie beispielsweise einem Kontextwechsel, gemessen. Diese Werte werden mit einem kommerziellen, stark optimierten AUTOSAR-OS verglichen. KW - Auftragsverwaltung (DV) KW - Automobilindustrie KW - Echtzeitbetriebssystem KW - Echtzeitsystem KW - eingebettetes System KW - Quellencodierung KW - Systemarchitektur KW - Task-Management KW - Validierung Y1 - 2014 SN - 978-3-9812696-5-9 SP - 154 EP - 161 CY - Landshut ER - TY - CHAP A1 - Hauser, Florian A1 - Mottok, Jürgen A1 - Gruber, Hans ED - Mottok, Jürgen T1 - Eye Tracking Metrics in Software Engineering T2 - Proceedings of the 3rd European Conference of Software Engineering Education (ECSEE'18); Seeon/ Bavaria Germany, 14.06.2018 -15.06.2018 N2 - This paper aims to provide an overview of the interdisciplinary combination of educational science, psychology, software engineering and the eye tracking methodology. The domain of software engineering is offering great potential for applied eye tracking research and in turn it can benefit from the possibilities of this upcoming technology as well. Nevertheless, software engineering has to struggle with some obstacles. These are namely the different terms, missing guidelines for experimental setups and a lack of common and standardized metrics. If eye tracking should be used in a broader way these problems must be solved. The main purpose of this paper is to list all eye tracking metrics which are relevant for software engineering and to give guidelines to help beginners by avoiding possible pitfalls. Y1 - 2018 SN - 9781450363839 U6 - https://doi.org/10.1145/3209087.3209092 SP - 39 EP - 44 PB - ACM CY - New York, NY ER - TY - CHAP A1 - Thomeczek, Ludwig A1 - Attenberger, Andreas A1 - Kolb, Johannes A1 - Matoušek, Václav A1 - Mottok, Jürgen ED - Unger, Herwig T1 - Betrachtungen zu Latenzquellen und deren Beobachtung in POSIX-Systemen am Beispiel von Container-Runtimes T2 - Echtzeit 2019 N2 - Die am weitesten verbreiteten autonomen Systeme der Zukunft sind aller Voraussicht nach intelligente Fahrzeuge, welche selbständig im Straßenverkehr navigieren und mit der Umgebung interagieren. Diese neuen Funktionen erfordern den Einsatz von performanten Mehrkernprozessoren sowie von komplexen (POSIX-kompatiblen) Betriebssystemen. Gleichzeitig erfordert der Einsatz im Automobil hohe funktionale Sicherheit (ASIL-Level), was unter anderem robuste Echtzeiteigenschaften der verwendeten Hard- und Software voraussetzt. Den Echtzeiteigenschaften steht die erhöhte Komplexität mit neuen Quellen für nichtdeterministische Latenzen gegenüber. In diesem Paper präsentieren wir eine Übersicht über diese neuen Einflussfaktoren, und vermessen anschließend Containerlaufzeitumgebungen und deren Latenzverhalten. Wir zeigen dabei, das Netzwerkbrücken unter Last erheblichen Einfluss (Faktor 4–5) auf die Netzwerklatenz ausüben können. Y1 - 2019 SN - 978-3-658-27807-6 U6 - https://doi.org/10.1007/978-3-658-27808-3_12 VL - 35 SP - 109 EP - 118 PB - Springer Fachmedien Wiesbaden CY - Wiesbaden ER - TY - JOUR A1 - Freiling, Felix A1 - Grimm, Rüdiger A1 - Großpietsch, Karl-Erwin A1 - Keller, Hubert B. A1 - Mottok, Jürgen A1 - Münch, Isabel A1 - Rannenberg, Kai A1 - Saglietti, Francesca T1 - Technische Sicherheit und Informationssicherheit. Unterschiede und Gemeinsamkeiten JF - Informatik-Spektrum Y1 - 2014 U6 - https://doi.org/10.1007/s00287-013-0748-2 VL - 37 IS - 1 SP - 14 EP - 24 PB - Springer ER - TY - CHAP A1 - Thomeczek, Ludwig A1 - Attenberger, Andreas A1 - Matoušek, Václav A1 - Mottok, Jürgen T1 - Latenzen von POSIX Betriebssystemen im Kontext von Hypervisoren in Real-Time Systemen T2 - Echtzeit und Sicherheit - Echtzeit 2018, Fachtagung des gemeinsamen Fachausschusses Echtzeitsysteme von Gesellschaft für Informatik e.V. (GI), VDI/VDE-Gesellschaft für Mess- und Automatisierungstechnik (GMA) und Informationstechnischer Gesellschaft im VDE (ITG), Boppard, 15. und 16. November 2018 N2 - Neu eingeführte Funktionen in der Automobilindustrie, wie zum Beispiel das autonome Fahren, erfordern den Einsatz von performanten Mehrkernprozessoren sowie von komplexen (POSIXkompatiblen) Betriebssystemen. Im Rahmen des branchenspezifischen Preisdrucks kommt es zudem zu einer Konsolidierung von Steuergeräten. Gleichzeitig erfordert der Einsatz im Automobil hohe funktionale Sicherheit (ASIL-Level), was unter anderem robuste Echtzeiteigenschaften der verwendeten Hard- und Software voraussetzt. Als Folge dessen werden zur Trennung von harten und weichen Echtzeitsystemen auf derselben Hardware Hypervisoren eingesetzt. Dieses Paper beleuchtet die Latenzauswirkungen diverser Softwarekonfigurationen auf Hardware der nächsten Generation mithilfe eines vorgestellten Testsetups und dessen Ergebnissen. Y1 - 2018 SN - 978-3-662-58095-0 SN - 978-3-662-58096-7 U6 - https://doi.org/10.1007/978-3-662-58096-7_11 SP - 99 EP - 108 ER - TY - CHAP A1 - Mucha, Matthias A1 - Mottok, Jürgen A1 - Krämer, Stefan T1 - Estimation of Worst Case Response Time Boundaries in Multi-Core Real-Time Systems T2 - 2017 International Conference on Applied Electronics (AE), 5-6 Sept. 2017, Pilsen N2 - We address a novel probabilistic approach to estimate the Worst Case Response Time boundaries of tasks. Multi-core real-time systems process tasks in parallel on two or more cores. Tasks in our contribution may preempt other tasks, block tasks with semaphores to access global shared resources, or migrate to another core. The depicted task behavior is random. The shape of collected response times of a task within a processing time is multimodal. Extreme Value approaches need unimodal response time distributions to estimate the Worst Case Response Time of tasks. The new proposed method derives a set of three task set shapes from the source task set. It is used to minimize the uncertainty of random task behavior by maximizing the coverage of possible Worst Case Response Times. The case study evaluates the new proposed estimation method by the use of dynamically generated random tasks with varying task properties. Y1 - 2017 SN - 978-80-261-0641-8 U6 - https://doi.org/10.23919/ae.2017.8053598 SN - 1803-7232 SP - 1 EP - 6 PB - IEEE ER - TY - JOUR A1 - De, Sangita A1 - Brada, Premek A1 - Mottok, Jürgen A1 - Niklas, Michael T1 - The Empirical Evaluation of Semantic Alignment Quality Metrics for Vehicle Domain Component Frameworks Interface Ontologies JF - FLAIRS 2021 : The 34th International FLAIRS Conference. Proceedings N2 - Semantic alignment of application software components’ ontologies represents a great interest in vehicle application domains that manipulate heterogeneous overlapping knowledge application frameworks. In the past few years, with the growth in the novel vehicle service requirements such as autonomous driving, V2X (Vehicle-to-Vehicle communication) and many others, automotive application software component models are becoming increasingly collaborative with other qualified cross-enterprise industrial partners to accomplish these complex service requirements. The most daunting impediment to this cross-enterprise collaboration is semantic interoperability. For efficient services collaboration through cross-enterprise semantic interoperability between the vehicle application frameworks’ software components, aligning the interface ontologies of these components by identifying the depth of semantic alignment relationships between the concepts of the interface ontologies is the major focus of this paper. In contrast to several existing ontology structural metrics, this work defines, evaluates and validates ontology metrics to measure the depth of semantic alignment between the vehicle domain software component frameworks’ interface ontological models. To emphasize the substantial role of semantic alignment of software component frameworks’ interface ontologies in semantic interoperability, a typical vehicle domain case study involving vehicle applications is considered for demonstration. Y1 - 2021 U6 - https://doi.org/10.32473/flairs.v34i1.128512 VL - 34 IS - 1 PB - LibraryPress@UF ER - TY - JOUR A1 - Schmid, Michael A1 - Fritz, Florian A1 - Mottok, Jürgen T1 - Fine-grained parallelism framework with predictable work-stealing for real-time multiprocessor systems JF - Journal of Systems Architecture N2 - Lately, parallel task models have received much attention in the development of real-time multiprocessor systems, as they allow highly compute-intensive tasks to have shorter deadlines which is very much required in modern reactive systems. However, missing modularity and portability can make parallel programming a cumbersome endeavor. As a consequence, compute-intensive sectors in the desktop and server segment have relied on parallelism frameworks such as Intel Threading Building Blocks, Cilk and OpenMP. These parallelism frameworks, however, are optimized for decent average case performance and consequently, do not meet the strict requirements imposed by real-time systems. In this paper, we present a proof-of-concept parallelism framework which was implemented in particular for soft real-time systems and having tight timing and safety requirements of such critical systems in mind. The proposed runtime system implements static memory allocation in a work-stealing environment that conforms to the strict space and tight probabilistic time bounds of work-stealing schedulers. Furthermore, we evaluate the performance of this framework by conducting multiprogrammed benchmarks on a real-time embedded multicore architecture. Y1 - 2022 U6 - https://doi.org/10.1016/j.sysarc.2022.102393 N1 - Corrigendum: https://www.sciencedirect.com/science/article/pii/S1383762123000528?via%3Dihub VL - 124 IS - March PB - Elsevier ER - TY - JOUR A1 - Joseph, Saskia A1 - Schumm, Michael A1 - Rummel, Otmar A1 - Soska, Alexander A1 - Renschke, Michael A1 - Mottok, Jürgen A1 - Niemetz, Michael A1 - Schroll-Decker, Irmgard T1 - Teaching finite state machines with case method and role play JF - 2014 IEEE Global Engineering Education Conference (EDUCON 2014) : Istanbul, Turkey, 3 - 5 April 2014 N2 - The professional requirements in Software Engineering have become highly volatile due to the complexities of project development and rapid and innovative changes occurring in the field. Therefore, the development of inter-personal and social competences has gained central importance in the training of software developers. This paper will present a concept allowing to acquire competences by using Case Method and Role Play as instruments in several lectures of Software Engineering. By approaching the issue of competence acquisition on a technical as well as on an educational and social level, life-long learning is facilitated and supported. KW - Case Method KW - competences KW - learning arrangement KW - life-long learning KW - Role Play Y1 - 2013 U6 - https://doi.org/10.1109/EduCon.2013.6530275 SP - 1302 EP - 1305 PB - IEEE ER - TY - CHAP A1 - Pozzobon, Enrico A1 - Renner, Sebastian A1 - Mottok, Jürgen A1 - Matoušek, Václav T1 - An optimized Bitsliced Masked Adder for ARM Thumb-2 Controllers T2 - 27th International Conference on Applied Electronics (AE): Sep 6, 2022 - Sep 7, 2022, Pilsen, Czech Republic N2 - The modular addition is used as a non-linear operation in ARX ciphers because it achieves the requirement of introducing non-linearity in a cryptographic primitive while only taking one clock cycle to execute on most modern architectures. This makes ARX ciphers especially fast in software implementations, but comes at the cost of making it harder to protect against side-channel information leakages using Boolean masking: the best known 2-shares masked adder for ARM Thumb micro-controllers takes 83 instructions to add two 32-bit numbers together. Our approach is to operate in bitsliced mode, performing 32 additions in parallel on a 32-bit microcontroller. We show that, even after taking into account the cost of bitslicing before and after the encryption, it is possible to achieve a higher throughput on the tested ciphers (CRAX and ChaCha20) when operating in bitsliced mode. Furthermore, we prove that no first-order information leakage is happening in either simulated power traces and power traces acquired from real hardware, after sufficient countermeasures are put into place to guard against pipeline leakages. KW - ARM Thumb KW - bitsliced KW - side-channel KW - Boolean masking Y1 - 2022 U6 - https://doi.org/10.1109/AE54730.2022.9919884 PB - IEEE ER - TY - CHAP A1 - Lalo, Erjola A1 - Sailer, Andreas A1 - Mottok, Jürgen A1 - Siemers, Christian T1 - Overhead-Aware Schedule Synthesis for Logical Execution Time (LET) in Automotive Systems T2 - 2022 IEEE 35th International System-on-Chip Conference (SOCC): 05-08 September 2022, Belfast, United Kingdom N2 - The Logical Execution Time (LET) has recently been integrated in multi-core automotive systems to ensure timing and dataflow determinism. Although buffering mechanisms are introduced to incorporate LET semantics, they do not guarantee that tasks are executed within their LET frames. In fact, LET and buffering semantics are violated if scheduling is not designed to execute all tasks within their LET frames and in a specific order. In this paper, we describe a scheduling synthesis technique for Fixed-Priority Scheduling (FPS) to achieve resource-efficient execution of LET systems. The proposed approach considers LET semantics, scheduling overheads, and delays caused by operating system operations and provides the possibility to optimize the schedule with respect to aspects like scheduling overheads. Our performance and feasibility evaluation shows that the proposed algorithm provides results in a reasonable amount of time for models of complex industrial applications. Thus, the integration of the proposed algorithm into an automated process is of high benefit to accelerate the development of vehicle applications. Y1 - 2022 SN - 978-1-6654-5985-3 U6 - https://doi.org/10.1109/SOCC56010.2022.9908103 SP - 1 EP - 6 PB - IEEE ER - TY - CHAP A1 - Frauenschläger, Tobias A1 - Mottok, Jürgen T1 - Security-Gateway for SCADA-Systems in Critical Infrastructures T2 - 27th International Conference on Applied Electronics (AE): 06-07 September 2022, Pilsen, CZ N2 - Supervisory Control and Data Acquisition (SCADA) systems are used to control and monitor components within the energy grid, playing a significant role in the stability of the system. As a part of critical infrastructures, components in these systems have to fulfill a variety of different requirements regarding their dependability and must also undergo strict audit procedures in order to comply with all relevant standards. This results in a slow adoption of new functionalities. Due to the emerged threat of cyberattacks against critical infrastructures, extensive security measures are needed within these systems to protect them from adversaries and ensure a stable operation. In this work, a solution is proposed to integrate extensive security measures into current systems. By deploying additional security-gateways into the communication path between two nodes, security features can be integrated transparently for the existing components. The developed security-gateway is compliant to all regulatory requirements and features an internal architecture based on the separation-of-concerns principle to increase its security and longevity. The viability of the proposed solution has been verified in different scenarios, consisting of realistic field tests, security penetration tests and various performance evaluations. KW - Critical Infrastructure KW - Certification KW - Supervisory Control and Data Acquisition KW - Security KW - Dependability Y1 - 2022 U6 - https://doi.org/10.1109/AE54730.2022.9920070 PB - IEEE ER - TY - CHAP A1 - Schmid, Michael A1 - Mottok, Jürgen T1 - Investigation of Scheduling Algorithms for DAG. Tasks through Simulations T2 - ERTS 2022, 11th European Congress Embedded Real Time Systems: 1-2 June, Toulouse, France N2 - In the real-time systems sector, various task models and corresponding tests exist to model and verify the schedulability of task sets on the system at hand. While those models and schedulability tests have intensively been studied from a theoretical point of view, it is hard to ma e use of them to compare the actual execution behavior of scheduling algorithms on a real system. In contrast to schedulability tests, simulators can help to investigate the performance of specific scheduling algorithms. One of the most generalized task models to describe parallel tasks is the Directed Acyclic Graph model that allows to represent tasks as a series of subtasks that depict the potentially parallel computations and precedence constraints that denote the order in which the subtasks are allowed to execute. In this paper, we investigate various scheduling algorithms for the Directed Acyclic Graph model. For that, we first recapitulate the examined scheduling algorithms in detail and point out relevant differences. Subsequently, we present the evaluation of different global and federated scheduling algorithms using fine-grained parallel tasks. To this end, we generate random Directed Acyclic Graph tasks and simulate their execution on multiprocessor systems using scheduling algorithms such as global rate-monotonic and semi-federated scheduling as well as global scheduling policies using the thread pool model. KW - real-time KW - scheduling KW - task models KW - simulation Y1 - 2022 UR - https://hal.archives-ouvertes.fr/hal-03700472/document ER -