TY - CHAP A1 - Steffens, Oliver A1 - Szabó, Peter A1 - Lenz, Michael A1 - Farkas, Gábor T1 - Thermal transient characterization methodology for single-chip and stacked structures BT - Best Paper Award T2 - Semiconductor Thermal Measurement and Management Symposium, 2005 N2 - High-power semiconductor packages typically exhibit a 3D heat flow, resulting in large lateral changes in chip and case surface temperature. For single-chip devices we propose to use an unambiguous definition for the junction-to-case thermal resistance as a key parameter, based on a transient measurement technique with much higher repeatability, also for very low thermal resistances compared to a two-point thermal resistance measurement. The technique is illustrated on thermal transient measurements of power MOSFETs. A comparison between different thermal coupling to the ambient is used to demonstrate the method's capability to reveal even subtle internal details of the package. The concept is extended to multichip and stacked-chip structures, where transfer impedances have to be introduced. Here, the dynamic properties of the package are important and complex impedance mapping is the proper way to characterize the package. KW - Thermal resistance KW - Temperature KW - Electrical resistance measurement KW - Impedance KW - Assembly KW - Semiconductor device packaging KW - Surface resistance KW - Measurement techniques KW - MOSFETs Y1 - 2005 U6 - https://doi.org/10.1109/STHERM.2005.1412198 SN - 1065-2221 SP - 313 EP - 321 PB - IEEE ER -