TY - GEN A1 - Renner, Sebastian A1 - Pozzobon, Enrico A1 - Mottok, Jürgen T1 - Current and Future Efforts in Benchmarking NIST LWC Ciphers T2 - 4th Lightweight Cryptography Workshop 2020 at NIST, Gaithersburg, USA Y1 - 2020 UR - https://csrc.nist.gov/CSRC/media/Presentations/efforts-in-benchmarking-lwc-ciphers/images-media/session-4-renner-current-future-benchmarking.pdf ER - TY - CHAP A1 - Renner, Sebastian A1 - Pozzobon, Enrico A1 - Mottok, Jürgen ED - Meng, Weizhi T1 - A Hardware in the Loop Benchmark Suite to Evaluate NIST LWC Ciphers on Microcontrollers T2 - Information and Communications Security: 22nd International Conference, ICICS 2020, Copenhagen, Denmark, August 24-26, 2020, Proceedings N2 - The National Institute of Standards and Technology (NIST) started the standardization process for lightweight cryptography algorithms in 2018. By the end of the first round, 32 submissions have been selected as 2nd round candidates. NIST allowed designers of 2nd round submissions to provide small updates on both their specifications and implementation packages. In this work, we introduce a benchmarking framework for evaluating the performance of NIST Lightweight Cryptography (LWC) candidates on embedded platforms. We show the features and application of the framework and explain its design rationale. Moreover, we provide information on how we aim to present up-to-date performance figures throughout the NIST LWC competition. In this paper, we present an excerpt of our software benchmarking results regarding speed and memory requirements of selected ciphers. All up-to-date results, including benchmarking different test cases for multiple variants of each 2nd round algorithm on five different microcontrollers, are periodically published to a public website. While initially only the reference implementations were available, the ability of automatically testing the performance of the candidate algorithms on multiple platforms becomes especially relevant as more optimized implementations are developed. Finally, we show how the framework can be extended in different directions: support for more target platforms can be easily added, different kinds of algorithms can be tested, and other test metrics can be acquired. The focus of this paper should rather lay on the framework design and testing methodology than on the current results, especially for reference code. KW - Lightweight cryptography KW - Benchmarking KW - Embedded systems KW - RISC-V Y1 - 2020 U6 - https://doi.org/10.1007/978-3-030-61078-4_28 SP - 495 EP - 509 PB - Springer CY - Cham ER - TY - CHAP A1 - Renner, Sebastian A1 - Pozzobon, Enrico A1 - Mottok, Jürgen A1 - Hackenberg, Rudolf T1 - Benchmarking Software Implementations of 1st Round Candidates of the NIST LWC Project on Microcontrollers T2 - 3rd Lightweight Cryptography Workshop at NIST, Gaithersburg, USA N2 - This paper introduces a custom framework for benchmarking software implementations from the National Institute of Standards and Technology (NIST) Lightweight Cryptography (LWC) project on embedded devices. We present the design and core functions of the framework and apply it to various NIST LWC authenticated encryption with associated data (AEAD) ciphers. Altogether, we evaluate the speed of 213 submitted algorithm vari-ants on four different microcontroller units (MCUs), including 32 bit ARM and 8 bit AVR architectures. To allow a more meaningful comparison, we also conduct code size tests on all four boards and RAM utilization tests on one test platform. Y1 - 2019 UR - https://csrc.nist.gov/CSRC/media/Events/lightweight-cryptography-workshop-2019/documents/papers/benchmarking-software-implementations-lwc2019.pdf ER - TY - JOUR A1 - Weiss, Nils A1 - Pozzobon, Enrico A1 - Mottok, Jürgen A1 - Matoušek, Václav T1 - Automated Reverse Engineering of CAN Protocols JF - Neural Network World N2 - Car manufacturers define proprietary protocols to be used inside their vehicular networks, which are kept an industrial secret, therefore impeding independent researchers from extracting information from these networks. This article describes a statistical and a neural network approach that allows reverse engineering proprietary controller area network (CAN)-protocols assuming they were designed using the data base CAN (DBC) file format. The proposed algorithms are tested with CAN traces taken from a real car. We show that our approaches can correctly reverse engineer CAN messages in an automated manner. Y1 - 2021 U6 - https://doi.org/10.14311/NNW.2021.31.015 SN - 1210-0552 VL - 31 IS - 4 SP - 279 EP - 295 ER - TY - CHAP A1 - Pozzobon, Enrico A1 - Renner, Sebastian A1 - Mottok, Jürgen A1 - Matoušek, Václav T1 - An optimized Bitsliced Masked Adder for ARM Thumb-2 Controllers T2 - 27th International Conference on Applied Electronics (AE): Sep 6, 2022 - Sep 7, 2022, Pilsen, Czech Republic N2 - The modular addition is used as a non-linear operation in ARX ciphers because it achieves the requirement of introducing non-linearity in a cryptographic primitive while only taking one clock cycle to execute on most modern architectures. This makes ARX ciphers especially fast in software implementations, but comes at the cost of making it harder to protect against side-channel information leakages using Boolean masking: the best known 2-shares masked adder for ARM Thumb micro-controllers takes 83 instructions to add two 32-bit numbers together. Our approach is to operate in bitsliced mode, performing 32 additions in parallel on a 32-bit microcontroller. We show that, even after taking into account the cost of bitslicing before and after the encryption, it is possible to achieve a higher throughput on the tested ciphers (CRAX and ChaCha20) when operating in bitsliced mode. Furthermore, we prove that no first-order information leakage is happening in either simulated power traces and power traces acquired from real hardware, after sufficient countermeasures are put into place to guard against pipeline leakages. KW - ARM Thumb KW - bitsliced KW - side-channel KW - Boolean masking Y1 - 2022 U6 - https://doi.org/10.1109/AE54730.2022.9919884 PB - IEEE ER - TY - GEN A1 - Renner, Sebastian A1 - Pozzobon, Enrico A1 - Mottok, Jürgen T1 - 3rd Round Ciphers Evaluation on Microcontrollers T2 - Lightweight Cryptography Workshop (virtual): May 9-11 2022 Y1 - 2022 UR - https://www.nist.gov/video/day-1-part-2-lightweight-cryptography-workshop-2022 PB - National Institute of Standards and Technology (NIST) CY - Gaithersburg ER - TY - CHAP A1 - Renner, Sebastian A1 - Pozzobon, Enrico A1 - Mottok, Jürgen ED - Li, Wenjuan ED - Furnell, Steven ED - Meng, Weizhi T1 - The Final Round: Benchmarking NIST LWC Ciphers on Microcontrollers T2 - Attacks and Defenses for the Internet-of-Things, 5th International Workshop, ADIoT 2022: Copenhagen, Denmark, September 30, 2022, Revised Selected Papers N2 - In this work, we present our benchmarking results for the ten finalist ciphers of the Lightweight Cryptography (LWC) project initiated by National Institute of Standards and Technology (NIST). We evaluate the speed and code size of various software implementations on five different platforms featuring four different architectures. Moreover, we benchmark the dynamic memory utilization of the remaining NIST LWC algorithms on one 32-bit ARM controller. We describe our test cases and methodology and provide some information regarding the design and properties of the finalists before showing and discussing our results. Altogether, we evaluated almost 300 implementations of the 3rd round candidates and pick the most appropriate and best (primary) implementation of each cipher for our comparisons. We include a variant of AES-GCM in our benchmarking in order to be able to compare the state-of-the-art to the novel LWC ciphers. Our research gives an overview over the performance of the latest software implementations of the NIST LWC finalists and shows under which circumstances which candidate is performing the best in our individual test cases. Additionally, we make all benchmarking results, the code for our test framework and every tested implementation available to the public to ensure a transparent testing process. Y1 - 2022 SN - 978-3-031-21311-3 U6 - https://doi.org/10.1007/978-3-031-21311-3_1 SP - 1 EP - 20 PB - Springer Nature CY - Cham ER - TY - CHAP A1 - Renner, Sebastian A1 - Pozzobon, Enrico A1 - Mottok, Jürgen ED - Li, Wenjuan ED - Furnell, Steven ED - Meng, Weizhi T1 - Evolving a Boolean Masked Adder Using Neuroevolution T2 - Attacks and Defenses for the Internet-of-Things, 5th International Workshop, ADIoT 2022: Copenhagen, Denmark, September 30, 2022, Revised Selected Papers N2 - The modular addition is a popular building block when designing lightweight ciphers. While algorithms mainly based on the addition can reach very high performance, masking their implementations results in a huge penalty. Since efficient protection against side-channel attacks is a requirement in lots of use cases, we focus on optimizing the Boolean masking of the modular addition. Contrary to recent related work, we target evolving a masked full adder instead of parts of a parallel prefix adder. We study how techniques typically found in neural network evolution and genetic algorithms can be adapted in order to help in evolving an efficiently masked adder. We customize a well-known neuroevolution algorithm, develop an optimized masked adder with our new approach and implement the ChaCha20 cipher on an ARM Cortex-M3 controller. We compare the performance of the protected neuroevolved implementation to solutions found by traditional search methods. Moreover, the leakage of our new solution is validated by a t-test conducted with a leakage simulator. We present under which circumstances our masked implementation outperforms related work and prove the feasibility of successfully using neuroevolution when searching for complex Boolean networks. Y1 - 2022 SN - 978-3-031-21310-6 U6 - https://doi.org/10.1007/978-3-031-21311-3_2 SP - 21 EP - 40 PB - Springer Nature CY - Cham ER - TY - JOUR A1 - Pozzobon, Enrico A1 - Weiß, Nils A1 - Mottok, Jürgen A1 - Matoušek, Václav T1 - An evolutionary fault injection settings search algorithm for attacks on safe and secure embedded systems JF - Neural Network World (NNW) Y1 - 2023 U6 - https://doi.org/10.14311/NNW.2023.33.020 VL - 33 IS - 5 SP - 357 EP - 374 PB - Czech Technical University in Prague ER - TY - CHAP A1 - Pozzobon, Enrico A1 - Weiß, Nils A1 - Mottok, Jürgen A1 - Matoušek, Václav T1 - Fuzzy fault injection attacks against secure automotive bootloaders T2 - 21th escar Europe : The World's Leading Automotive Cyber Security Conference (Hamburg, 15. - 16.11.2023) N2 - Secure embedded bootloaders are the trust anchors for modern vehicles’ software. The secure software update process of ECUs is well-defined across the entire automotive industry. Every OEM has his own implementation, but follows the general software update process. This paper demonstrates code execution attacks by combining software and hardware weaknesses in secure automotive bootloaders. The attack can be performed entirely automated, no static code analysisis required. Random fault injection parameters were sufficient to obtain code execution in a reasonable time. All experiments were conducted with electromagnetic fault injection and without any hardware modifications of the targets. We successfully performed our attack on two entirely different gateway Electronic Control Units (ECUs) used in current vehicles (at the time of this research) from Volkswagen and BMW. As a result of this attack, consisting of a combination of a hardware and asoftware attack, the general secure software update process used in the automotive industry needs to be revised. Y1 - 2023 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:hbz:294-103817 PB - Ruhr-Universität Bochum ER -