TY - CHAP A1 - Lalo, Erjola A1 - Sailer, Andreas A1 - Mottok, Jürgen A1 - Siemers, Christian T1 - Overhead-Aware Schedule Synthesis for Logical Execution Time (LET) in Automotive Systems T2 - 2022 IEEE 35th International System-on-Chip Conference (SOCC): 05-08 September 2022, Belfast, United Kingdom N2 - The Logical Execution Time (LET) has recently been integrated in multi-core automotive systems to ensure timing and dataflow determinism. Although buffering mechanisms are introduced to incorporate LET semantics, they do not guarantee that tasks are executed within their LET frames. In fact, LET and buffering semantics are violated if scheduling is not designed to execute all tasks within their LET frames and in a specific order. In this paper, we describe a scheduling synthesis technique for Fixed-Priority Scheduling (FPS) to achieve resource-efficient execution of LET systems. The proposed approach considers LET semantics, scheduling overheads, and delays caused by operating system operations and provides the possibility to optimize the schedule with respect to aspects like scheduling overheads. Our performance and feasibility evaluation shows that the proposed algorithm provides results in a reasonable amount of time for models of complex industrial applications. Thus, the integration of the proposed algorithm into an automated process is of high benefit to accelerate the development of vehicle applications. Y1 - 2022 SN - 978-1-6654-5985-3 U6 - https://doi.org/10.1109/SOCC56010.2022.9908103 SP - 1 EP - 6 PB - IEEE ER - TY - CHAP A1 - Sailer, Andreas A1 - Schmidhuber, Stefan A1 - Deubzer, Michael A1 - Alfranseder, Martin A1 - Mucha, Matthias A1 - Mottok, Jürgen T1 - Optimizing the task allocation step for multi-core processors within autosar T2 - 2013 International Conference on Applied Electronics, IEEE, Pilsen, Czech Republic N2 - We present a model-based optimization approach for the task allocation problem in embedded multi-core systems. The information therefore is obtained from a system description in AUTOSAR and runtime measurements of the runnables in hardware traces. Based on this an initial software partitioning of runnables to tasks is created. We then use a genetic algorithm to create and evaluate solutions to the task allocation problem. Each solution is hereby evaluated using a discrete event-based simulation, which allows the evaluation with regard to real-time properties, resource consumption and data-communication overhead. The significance of our approach is then shown in a case-study. There, we optimize the task allocation of an embedded system, whose complexity is comparable to that of an actual system, on a multi-core processor. Finally, the results of the optimization are transferred to an ECU Configuration Description to enable further development in compliance with the AUTOSAR methodology. KW - AUTOSAR KW - Multi-Objective Optimization KW - Multi-Core KW - Goodness-of-fit KW - Task Allocation Y1 - 2013 UR - https://ieeexplore.ieee.org/document/6636524 ER - TY - CHAP A1 - Alfranseder, Martin A1 - Mucha, Matthias A1 - Schmidhuber, Stefan A1 - Sailer, Andreas A1 - Niemetz, Michael A1 - Mottok, Jürgen T1 - A modified synchronization model for dead-lock free concurrent execution of strongly interacting task sets in embedded systems T2 - 2013 International Conference on Applied Electronics (AE 2013), IEEE, 10-12 September 2013, Pilsen, Czech Republic N2 - Global scheduling algorithms are very promising for application in embedded real-time systems using multi-core controllers. In this paper we want to make a first step forward to apply such scheduling methods on real existing systems. Especially a new resource model is necessary to avoid deadlocks, as this goal can not be achieved by using the standard OSEK Priority Ceiling Protocol when shared global resources are in use. We also introduce the new metric mean Normalized Blocking Time in order to be able to compare locking mechanisms according to the timing effects of their blocking behavior. Finally we give a simulative application example of the new metric by the use of two different kinds of semaphore models and an example task set typical for existing embedded real-time systems in the automotive powertrain environment. Y1 - 2013 VL - 18 SP - 13 EP - 18 ER - TY - GEN A1 - Alfranseder, Martin A1 - Schmidhuber, Stefan A1 - Mucha, Matthias A1 - Sailer, Andreas A1 - Mottok, Jürgen T1 - How to improve the reactiveness and efficiency of embedded multicore systems by use of probabilistic simulation and optimization techniques: A case study BT - Invited Poster Session T2 - Advanced Research Workshop: Improving Disaster Resilience and Mitigation - New Means and Tools, Trends, Iasi Y1 - 2013 ER - TY - CHAP A1 - Sailer, Andreas A1 - Schmidhuber, Stefan A1 - Deubzer, Michael A1 - Mottok, Jürgen T1 - Amalthea – Plattform für kontinuierliche, modellbasierte Entwicklung T2 - Tagungsband, 6th Embedded Software Engineering, Kongress 2013, 2. bis 6. Dezember 2013, Sindelfingen Y1 - 2013 SP - 538 EP - 544 ER - TY - CHAP A1 - Sailer, Andreas A1 - Deubzer, Michael A1 - Lüttgen, Gerald A1 - Mottok, Jürgen T1 - CoreTAna: A Trace Analyzer for Reverse Engineering Real-Time Software T2 - IEEE 23rd International Conference on Software Analysis, Evolution, and Reengineering (SANER), March 14 to March 18 2016, Suita, Osaka, Japan N2 - With the availability of the AUTOSAR standard, model-driven methodologies are becoming established in theautomotive domain. However, the process of creating models ofexisting system components is often difficult and time consuming, especially when legacy code has to be re-used or informationabout the exact timing behavior is needed. In order to tackle thisreverse engineering problem, we present CoreTAna, a novel toolthat derives an AUTOSAR compliant model of a real-time systemfrom a dynamic analysis of its trace recordings. This paper givesan overview of CoreTAna's current features and discusses itsbenefits for reverse engineering. KW - AUTOSAR KW - tracing KW - profiling KW - timing model KW - reverse engineering Y1 - 2016 U6 - https://doi.org/10.1109/SANER.2016.36 ER - TY - CHAP A1 - Lalo, Erjola A1 - Weber, Raphael A1 - Sailer, Andreas A1 - Mottok, Jürgen A1 - Siemers, Christian T1 - On Solving Task Allocation and Schedule Generation for Time-Triggered LET Systems using Constraint Programming T2 - 32nd International Conference on Architecture of Computing Systems, ARCS Workshop 2019, 20-21 May 2019, Copenhagen, Denmark N2 - The amount of safety-critical embedded systems in automotive development is heavily growing. Ensuring their reliability not only increases the complexity of functions but also requires determinism at design and execution time, which is considerably challenging to fulfill and verify for multi-core processors. The Logical Execution Time (LET) is recently recognized in automotive industry as an approach for ensuring deterministic functional behavior. However, to decrease the manual design effort and time for deploying such complex systems to multi-core platforms and for ensuring their strict timing and safety requirements, automatic solutions are needed. This work presents a solution for allocating tasks to multi-core processors and generating a time-triggered schedule for embedded systems considering safety, timing, and LET semantics. The approach we propose solves both challenges by defining them as a Constraint Satisfaction Problem (CSP). To examine our CSP formulation, we use MiniZinc, which is a solver-independent constraint modeling language that can employ a variety of solvers. In a case study, we explore optimizations of an industrial system that are enabled by scheduling and task allocation design decisions. Further, the performance of the proposed solutions is evaluated based on large set of synthetically generated system models. Y1 - 2019 UR - https://ieeexplore.ieee.org/abstract/document/8836201 SP - 1 EP - 8 ER - TY - CHAP A1 - Mottok, Jürgen A1 - Alfranseder, Martin A1 - Schmidhuber, Stefan A1 - Mucha, Matthias A1 - Sailer, Andreas ED - Teodorescu, Horia-Nicolai ED - Kirschenbaum, Alan ED - Cojocaru, Svetlana ED - Bruderlein, Claude T1 - How to improve the reactiveness and efficiency of embedded multicore systems by use of probabilistic simulation and optimization techniques T2 - Improving Disaster Resilience and Mitigation - New Means and Tools. NATO Science for Peace and Security Series C: Environmental Security N2 - Safe and reliable multi-core technology becomes more and more important in the field of embedded systems. Today’s and future embedded systems require increasing performance while being more energy efficient. Moreover, the functional safety for these embedded systems has to be improved or developed completely new. In this chapter, we first address the challenges of embedded multi-core real-time systems. To raise the resilience of such systems we use the deadlock-free synchronization model of Block et al. (A flexible real-time locking protocol for multiprocessors. 2012 IEEE international conference on embedded and real-time computing systems and applications, vol 0, pp 47–56, 2007). The metric mean Normalized Blocking Time (mNBT) is hereby used to measure the timing effects of the blocking behavior of strongly interacting tasks. In a second step, we present a model-based approach to map the tasks of an embedded real-time system to the cores of a multi-core processor. Moreover, we derive an execution time model from runtime measurements of software functions. This information is then used to perform precise probabilistic simulations of different task-to-core mappings and evaluate them with regard to task response times, inter-task blocking overhead and load distribution. Subsequently, we integrate the probabilistic simulation within an optimization technique to systematically improve the task-to-core mapping. We conclude with a case-study, where we demonstrate the effectiveness of the presented approach by optimizing the task-to-core mapping of a practical automotive powertrain system. KW - Embed System KW - Functional Safety KW - Arrival Curve KW - Task Allocation Problem KW - Deadline Violation Y1 - 2014 U6 - https://doi.org/10.1007/978-94-017-9136-6_16 SP - 253 EP - 268 PB - Springer CY - Dodrecht ER - TY - CHAP A1 - Sailer, Andreas A1 - Schmidhuber, Stefan A1 - Deubzer, Michael A1 - Hobelsberger, Martin A1 - Mottok, Jürgen T1 - Requirements engineering for a continuous design flow and methodology T2 - 2nd Applied Research Conference 2012 (ARC 2012) 25./26. June 2012, Nuremberg Y1 - 2012 SN - 978-3-8440-1093-0 SP - 76 EP - 79 PB - Shaker CY - Aachen ER - TY - CHAP A1 - Schmidhuber, Stefan A1 - Sailer, Andreas A1 - Deubzer, Michael A1 - Hobelsberger, Martin A1 - Mottok, Jürgen T1 - Overview of the itea2-project amalthea T2 - 2nd Applied Research Conference 2012 (ARC 2012) 25./26. June 2012, Nuremberg Y1 - 2012 SN - 978-3-8440-1093-0 SP - 60 EP - 62 PB - Shaker CY - Aachen ER - TY - CHAP A1 - Martin, Felix A1 - Sailer, Andreas A1 - Deubzer, Michael A1 - Mottok, Jürgen T1 - Automatische Multicore-Echtzeitvalidierung – Ein Prozess für modellbasierte Softwareentwicklung T2 - Tagungsband 8th Embedded Software Engineering Kongress (ESE), 30.11. - 04.12.2015, Sindelfingen Y1 - 2015 ER - TY - CHAP A1 - Martin, Felix A1 - Sailer, Andreas A1 - Deubzer, Michael A1 - Mottok, Jürgen T1 - Automation of a Closed Loop Model-Based Development Process T2 - Applied Research Conference 2015 (ARC 2015), 3rd July 2015, Nürnberg Y1 - 2015 ER - TY - CHAP A1 - Sailer, Andreas A1 - Deubzer, Michael A1 - Lüttgen, Gerald A1 - Mottok, Jürgen T1 - Comparing Trace Recordings of Automotive Realtime Software T2 - RTNS '17: Proceedings of the 25th International Conference on Real-Time Networks and Systems, Grenoble, France, IEEE N2 - The process of engineering models of existing real-time system components is often difficult and time consuming, especially when legacy code has to be re-used or information about the exact timing behaviour is needed. In order to tackle this reverse engineering problem, we have developed the tool CoreTAna. CoreTAna derives an AUTOSAR compliant model of a real-time system by conducting dynamic analysis using trace recordings. Motivated by the challenge of assessing the quality of reverse engineered models of real-time software, we present a novel mathematical measure for comparing trace recordings from embedded real-time systems regarding their temporal behaviour. We also introduce a benchmark framework based on this measure, for evaluating reverse engineering tools such as CoreTAna. This considers common system architectures and also includes randomly generated systems and three systems of industrial automotive projects. Finally, an industrial case study demonstrates other use cases of our measure, such as impact analysis. Y1 - 2017 U6 - https://doi.org/10.1145/3139258.3139265 SP - 118 EP - 127 ER -