TY - CHAP A1 - Schubert, Martin J. W. T1 - Mixed Signal Modeling in VHDL by Distributed Local Iteration T2 - VHDL Form, Toledo, Spain, April 20-24, 1997 Y1 - 1997 ER - TY - CHAP A1 - Schubert, Martin J. W. T1 - Mixed Analog-Digital Signal Modeling Using Event-Driven VHDL T2 - X Brazilian Symposium on Integrated Circuit Design (SBCCI'97), August 25-27 1997, Porto Alegre, Brazil N2 - A method for solving networks containing generic analog components such as resistors, capacitors and inductors onan event driven time axis using digital VHDL is presented. The components are modeled as complex state machines communicating with their neighbors using INOUT type ports. The method takes advantage of simulation deltas to iterate without simulation-time consumption. A limited range of implicit equations can be solved this way. Y1 - 1997 UR - http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=50F6F0DA594FB90976CC1474581BC139?doi=10.1.1.508.3657&rep=rep1&type=pdf SP - 77 EP - 86 ER - TY - PAT A1 - Schubert, Martin J. W. T1 - Feedback-nach-Feedforward-Transformation zur Verhaltensmodellierung rückgekoppelter Verstärker Y1 - 1997 ER - TY - CHAP A1 - Schubert, Martin J. W. T1 - Operational Amplifier Modeling Using Event-Driven VHDL T2 - IEEE/VIUF International Workshops on Behavioral Modeling and Simulation (BMAS'97), October 20/21 1997, Washington D.C., USA N2 - A method to model high-gain feedback-loop analog amplifiers on an event driven timeaxis is presented. The demonstrator is coded in digital VHDL’93. In the event-driven scheme any node in the network must converge „on its own“ based on the information delivered from its neighbors, as no overall matrix is set up. For this reason signalloops with a loop gain larger than one are typically unstable. This communication presents a numerically stable generic model for high gain amplifiers with a userdefined feedback network. Non-ideal effects like offset or finite gain can be taken into account. Y1 - 1997 UR - https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.495.5356&rep=rep1&type=pdf ER - TY - CHAP A1 - Bartsch, Ernst A1 - Schubert, Martin J. W. T1 - Mixed Analog-Digital Circuit Modeling Using Event-Driven VHDL T2 - IEEE/VIUF International Workshops on Behavioral Modeling and Simulation (BMAS'97), Ocotober 20/21 1997, Washington D.C., USA N2 - The mixed-signal event-driven (MixED) method developed to simulate small portions of analog circuitry within a digital environment is demonstrated in a mixed signal application. The MixED models using concurrent iteration to account for analog nodes were coded and run in standard VHDL’93. Networks containing linear components such as sources, resistors, capacitors, inductors and operational amplifiers are presented. The possibility to manipulate resistors during runtime is used to simulate switches. Y1 - 1997 UR - https://hps.oth-regensburg.de/scm39115/homepage/research/mixed/mixed_publications/1997_bmas_circuit.pdf ER - TY - JOUR A1 - Lee, Wai-Kong A1 - Schubert, Martin J. W. A1 - Ooi, Boon Yaik A1 - Ho, Stanley Jian-Qin T1 - Multi-source energy harvesting and storage for floating wireless sensor network nodes with Long Range Communication Capability JF - IEEE Transactions on Industry Applications N2 - Wireless sensor networks are widely used for environmental monitoring in remote areas. They are mainly composed of wireless sensor nodes, usually powered by batteries with limited capacity, but are expected to communicate in long range and operate for extended time periods. To overcome these limitations, many energy harvesting techniques are proposed to power wireless nodes for prolonged operation, whereas multihop techniques are utilized to extend the communication range. In this paper, a novel floating device with multisource energy harvesting technology that can be used as a wireless sensor node is proposed. The long range communication between wireless sensor nodes and a gateway is established through LoRa technology. In addition to conventional solar panels, an energy harvesting technique based on thermoelectric generators exploiting thermal differences created between water surface and materials exposed to sunlight is proposed. Energy generated from photovoltaic and thermoelectric generators is combined to power the wireless sensor node. This floating device consumes 6.6216 Wh per day when used as a wireless sensor node for the collection and transmission of environmental data. The sensor node can operate on a water surface for at least 9.6 days when it is not exposed to sunlight. During a sunny day, the floating device can harvest 8.375 Wh from solar panels and 0.425 Wh from thermoelectric generation. In other words, the floating device harvests sufficient energy to be self-sustaining during sunny days. KW - Wireless sensor networks KW - Energy harvesting KW - floating device KW - LoRa KW - sensor node KW - solar energy KW - thermoelectric generation Y1 - 2018 U6 - https://doi.org/10.1109/TIA.2018.2799 VL - 54 IS - 3 SP - 2606 EP - 2615 PB - IEEE ER - TY - CHAP A1 - Ooi, Boon Yaik A1 - Lee, Wai-Kong A1 - Schubert, Martin J. W. A1 - Ooi, Yu-Wei A1 - Chin, Chee-Yang A1 - Woo, Wing-Hon T1 - A Flexible and Reliable Internet-of-Things Solution for Real-Time Production Tracking T2 - IEEE Industrial Electronics and Applications Conference (IEACon): 22.11.2021 - 23.11.2021, Penang, Malaysia N2 - The concept of Industrial Revolution 4.0 (IR4.0) has sparked the urgency of many manufacturers to revisit their manufacturing processes and search for opportunities to further improved their production output. Unfortunately, it is difficult to improve a process with inadequate data. Many of the SMEs in developing countries are still using manufacturing machines from the yesteryears which do not have computational and connectivity capabilities. Therefore, we developed an end-to-end Internet-of-Things (IoT) solution, which reliably tracks the production performance of manufacturing machines. This paper elaborates on the designs and the rationale behind it. As of the writing of this paper, our IoT system has been deployed in real manufacturing environment and has been running for approximately 90 days on a 24/7 basis without data lost. KW - industry 4.0 KW - IoT KW - production tracking KW - Smart Manufacturing Y1 - 2021 SN - 978-1-7281-9253-6 U6 - https://doi.org/10.1109/IEACon51066.2021.9654672 SP - 270 EP - 275 PB - IEEE ER - TY - CHAP A1 - Schubert, Martin J. W. A1 - Lee, Wai-Kong A1 - Ooi, Boon Yaik T1 - Quantization and Sampling Effects in Fast Digitally Controlled Switch-Mode DC/DC Buck Converters T2 - 2021 IEEE Industrial Electronics and Applications Conference (IEACon): 22.11.2021 - 23.11.2021, Penang, Malaysia N2 - Software-defined control of DC/DC switch mode power converters features unequaled flexibility compared to analog control. For fast switching converters as recently used for low power applications, digital control may cause steady-state oscillations known as limit cycles. This effect based on a quantized duty cycle is compared to other aberrations such as output ripple voltage, which is inherent to any pulse-width modulator. A distinction is made between DC and AC errors. The latter are divided into synchronous and asynchronous output voltage disturbances. Synchronous AC errors are composed of the switching frequency and its harmonics. KW - aberrations due to digitization KW - digital pulse-width modulation (DPWM) KW - low power DC/DC buck conversion KW - output voltage sampling Y1 - 2021 SN - 978-1-7281-9253-6 U6 - https://doi.org/10.1109/IEACon51066.2021.9654272 SP - 56 EP - 61 PB - IEEE ER - TY - CHAP A1 - Schubert, Martin J. W. A1 - Höfflinger, Bernd A1 - Zingg, René P. T1 - A New Analytical Charge Model for the Dual-Gate-Controlled Thin-Film SOI MOSFET T2 - Superlattices and Microstructures N2 - An analytical model for dual-gate-controlled SOI MOSFETs is presented, assuming uniformly doped p-silicon films. It is restricted to electron inversion layers and depletion regions, neglecting hole densities. It allows to account for the spatial description of electronic quantities in the silicon film. Due to the non-linearities of the semiconductor equations the model parameters must be extracted iteratively. Some applications are presented to demonstrate the usefulness of the model. Y1 - 1990 U6 - https://doi.org/10.1016/0749-6036(90)90218-V VL - 7 IS - 4 SP - 323 EP - 326 PB - Elsevier ER - TY - CHAP A1 - Schubert, Martin J. W. A1 - Blödel, J. A1 - Conradi, P. A1 - Lafosse, P. A1 - Nebel, W. A1 - Neusser, S. A1 - Ryba, M. A1 - Schröder, D. T1 - Extending EDIF for Technology Data T2 - EDIF World Conference, 1989, San Jose, CA, USA, 11.-14. September Y1 - 1989 ER - TY - THES A1 - Schubert, Martin J. W. T1 - Eindimensionale Modellierung von SOI MOSFETs Y1 - 1991 CY - Hamburg ER - TY - JOUR A1 - Schubert, Martin J. W. A1 - Höfflinger, Bernd A1 - Schröder, D. A1 - Zingg, René P. T1 - 1D Modeling of SOI MOSFETs Using Distinct Quasi-Fermi Potentials JF - Microelectronic Engineering N2 - Distinct electron and hole quasi-Fermi potentials, øf,n and øf,p, are included into a one-dimensional SOI MOSFET model that accounts for finite inversion and depletion layer thicknesses. The inclusion of øf,n, øf,p in the nonlinear analytical model is demonstrated to describe phenomena like kink effect and the multistable-charge-controlled-memory effect (MCCM) in SOI MOSFETs. The calculation of øf,p(t) depends on the device history and generation/recombination rates. Y1 - 1991 U6 - https://doi.org/10.1016/0167-9317(91)90221-X VL - 15 IS - 1-4 SP - 237 EP - 240 ER - TY - JOUR A1 - Schubert, Martin J. W. A1 - Höfflinger, Bernd A1 - Zingg, René P. T1 - An Analytical Model for Strongly Inverted and Accumulated Silicon Films JF - Solid-State Electronics N2 - An analytical model for the spatial distribution of potential, electric field and carrier densities is presented, assuming uniform doping density and constant quasi-Fermi potentials in the direction of modeling. Starting from the current relations a differential equation respecting two-dimensional effects is developed and solved approximately by decomposition in three regions with different preconditions: (a) flatband region, (b) constant spacecharge density and (c) strong inversion or accumulation. Inaccuracies arise mainly from violated preconditions at the interfaces between the different regions. Two-dimensional effects are respected in the analytical model of (b) only but they influence region (c) by means of boundary conditions at the interface of (b) and (c). The investigations of this paper are focused to region (c). This part of our model is identical to the model of Hauser and Littlejohn[1]. They integrated a simplified form of the semiconductor-Poisson equation twice but were restricted to one-dimensional applications and thermal equilibrium. Our derivation allows for large electric fields and current densities perpendicular to the direction of modeling. From analytical considerations confirmed by numerical experiments we suggest preference to the gradual channel condition, with x and y defined according to Fig. 1. This definition allows the potentials to vary significantly with respect to y. We found that this holds for the quasi-Fermi potentials also. Furthermore an empirical model for the maximum width of strong-inversion layers in uniformly doped silicon films is presented in eqn (46). Y1 - 1990 U6 - https://doi.org/10.1016/0038-1101(90)90136-3 VL - 33 IS - 12 SP - 1553 EP - 1567 PB - Elsevier ER - TY - CHAP A1 - Declerq, Michel A1 - Schubert, Martin J. W. A1 - Clément, F. T1 - 5V-to-75V CMOS Output Interfaces T2 - Proceedings of the1993 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 24-26 1993, San Francisco, CA, USA N2 - A family of CMOS low- to high-voltage output interface circuits based on a standard, unmodified low-voltage CMOS technology is described. Using only thin-oxide high-voltage (HV) devices with reduced V/sub GS/ (gate-to-source voltage) swing, it makes use of level-shift techniques to meet the constraints on the gate control signals. These static circuits permit the full output voltage swing of V/sub DDH/, while keeping the V/sub GS/ swing of the output devices within the safety limits, including during HV supply transients. Using a standard 2- mu m n-well CMOS technology, reliable, reproducible V/sub DS/ breakdown voltages as high as 120 V and 80 V have been obtained for HV-nMOS and HV-pMOS devices, respectively.< > Y1 - 1993 U6 - https://doi.org/10.1109/ISSCC.1993.280014 SP - 162 EP - 163 ER - TY - CHAP A1 - Declerq, Michel A1 - Clément, F. A1 - Schubert, Martin J. W. A1 - Harb, Adnan A1 - Dutoit, Michel T1 - Design and Optimization of High-Voltage CMOS Devices Compatible wih a Standard 5V CMOS Technology T2 - Proceedings of IEEE Custom Integrated Circuits Conference, May 9-12 1993, San Diego, CA, USA N2 - High-voltage n- and p-MOSFETs fully compatible with a standard 5 V CMOS technology have been designed, optimized, and fabricated. No process changes are required. By modifying the logical equations generating one of the physical masks from the design masks, a p-type buffer region for the high-voltage p-MOS was easily implemented. This modification does not affect the low-voltage part of the circuits. These high-voltage devices have been used successfully as output drivers in semicustom arrays, and as building blocks for custom low- to high-voltage output interfaces. Aspects of reliability, device protection, and circuit design techniques are addressed. Y1 - 1993 SN - 0-7803-0826-3 U6 - https://doi.org/10.1109/CICC.1993.590766 SP - 24.6.1 EP - 24.6.4 ER - TY - JOUR A1 - Schubert, Martin J. W. A1 - Höfflinger, Bernd A1 - Zingg, René P. T1 - A One-Dimensional Analytical Model for the Dual-Gate-Controlled Thin-Film SOI MOSFET JF - IEEE Electron Device Letters N2 - A one-dimensional analytical model for dual-gate-controlled SOI MOSFETs is presented and applied to a stacked p-channel MOSFET fabricated by epitaxial lateral overgrowth (ELO). The authors found and modeled a nonlinear dependence of front-gate threshold voltage on back-gate voltage if threshold is defined by a constant current instead of a constant silicon-surface potential. It is demonstrated by comparison of subthreshold slopes that surface potentials are not pinned to the onset of strong inversion or accumulation. Accurate one-dimensional modeling is a necessity for device characterization and a precondition for general SOI models for circuit simulation.< > Y1 - 1991 U6 - https://doi.org/10.1109/55.116927 VL - 12 IS - 9 SP - 489 EP - 491 ER - TY - PAT A1 - Declerq, Michel A1 - Schubert, Martin J. W. T1 - Circuit Intermédiaire entre un Circuit Logique à Basse-Tension et un Etage de Sortie à Haute-Tension Réalisés dans une Technologie CMOS Standard N2 - La présente invention concerne un circuit intermédiaire entre un circuit logique a basse tension et un étage de sortie à haute tension réalisés dans une technologie CMOS standard. L'étage de sortie (20) comporte deux transistors respectivement à canal N et à canal P, réalisés selon une technologie CMOS standard. Le circuit intermédiaire comporte un translateur de niveau de tension (21) couplé entre un circuit logique d'entrée SL et ledit étage de sortie (20). Ce translateur de niveau de tension (21) est réalisé selon une technologie CMOS standard et est constitué d'au moins deux blocs de base identiques formant des miroirs de tension interconnectés de façon croisée. Ce circuit est utilisé pour commander des transducteurs, des écrans plasma et des actionneurs électromécaniques. Y1 - 1992 ER -