TY - THES A1 - Schubert, Martin J. W. T1 - Eindimensionale Modellierung von SOI MOSFETs Y1 - 1991 CY - Hamburg ER - TY - JOUR A1 - Schubert, Martin J. W. A1 - Höfflinger, Bernd A1 - Schröder, D. A1 - Zingg, René P. T1 - 1D Modeling of SOI MOSFETs Using Distinct Quasi-Fermi Potentials JF - Microelectronic Engineering N2 - Distinct electron and hole quasi-Fermi potentials, øf,n and øf,p, are included into a one-dimensional SOI MOSFET model that accounts for finite inversion and depletion layer thicknesses. The inclusion of øf,n, øf,p in the nonlinear analytical model is demonstrated to describe phenomena like kink effect and the multistable-charge-controlled-memory effect (MCCM) in SOI MOSFETs. The calculation of øf,p(t) depends on the device history and generation/recombination rates. Y1 - 1991 U6 - https://doi.org/10.1016/0167-9317(91)90221-X VL - 15 IS - 1-4 SP - 237 EP - 240 ER - TY - JOUR A1 - Schubert, Martin J. W. A1 - Höfflinger, Bernd A1 - Zingg, René P. T1 - An Analytical Model for Strongly Inverted and Accumulated Silicon Films JF - Solid-State Electronics N2 - An analytical model for the spatial distribution of potential, electric field and carrier densities is presented, assuming uniform doping density and constant quasi-Fermi potentials in the direction of modeling. Starting from the current relations a differential equation respecting two-dimensional effects is developed and solved approximately by decomposition in three regions with different preconditions: (a) flatband region, (b) constant spacecharge density and (c) strong inversion or accumulation. Inaccuracies arise mainly from violated preconditions at the interfaces between the different regions. Two-dimensional effects are respected in the analytical model of (b) only but they influence region (c) by means of boundary conditions at the interface of (b) and (c). The investigations of this paper are focused to region (c). This part of our model is identical to the model of Hauser and Littlejohn[1]. They integrated a simplified form of the semiconductor-Poisson equation twice but were restricted to one-dimensional applications and thermal equilibrium. Our derivation allows for large electric fields and current densities perpendicular to the direction of modeling. From analytical considerations confirmed by numerical experiments we suggest preference to the gradual channel condition, with x and y defined according to Fig. 1. This definition allows the potentials to vary significantly with respect to y. We found that this holds for the quasi-Fermi potentials also. Furthermore an empirical model for the maximum width of strong-inversion layers in uniformly doped silicon films is presented in eqn (46). Y1 - 1990 U6 - https://doi.org/10.1016/0038-1101(90)90136-3 VL - 33 IS - 12 SP - 1553 EP - 1567 PB - Elsevier ER - TY - CHAP A1 - Declerq, Michel A1 - Schubert, Martin J. W. A1 - Clément, F. T1 - 5V-to-75V CMOS Output Interfaces T2 - Proceedings of the1993 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 24-26 1993, San Francisco, CA, USA N2 - A family of CMOS low- to high-voltage output interface circuits based on a standard, unmodified low-voltage CMOS technology is described. Using only thin-oxide high-voltage (HV) devices with reduced V/sub GS/ (gate-to-source voltage) swing, it makes use of level-shift techniques to meet the constraints on the gate control signals. These static circuits permit the full output voltage swing of V/sub DDH/, while keeping the V/sub GS/ swing of the output devices within the safety limits, including during HV supply transients. Using a standard 2- mu m n-well CMOS technology, reliable, reproducible V/sub DS/ breakdown voltages as high as 120 V and 80 V have been obtained for HV-nMOS and HV-pMOS devices, respectively.< > Y1 - 1993 U6 - https://doi.org/10.1109/ISSCC.1993.280014 SP - 162 EP - 163 ER - TY - CHAP A1 - Declerq, Michel A1 - Clément, F. A1 - Schubert, Martin J. W. A1 - Harb, Adnan A1 - Dutoit, Michel T1 - Design and Optimization of High-Voltage CMOS Devices Compatible wih a Standard 5V CMOS Technology T2 - Proceedings of IEEE Custom Integrated Circuits Conference, May 9-12 1993, San Diego, CA, USA N2 - High-voltage n- and p-MOSFETs fully compatible with a standard 5 V CMOS technology have been designed, optimized, and fabricated. No process changes are required. By modifying the logical equations generating one of the physical masks from the design masks, a p-type buffer region for the high-voltage p-MOS was easily implemented. This modification does not affect the low-voltage part of the circuits. These high-voltage devices have been used successfully as output drivers in semicustom arrays, and as building blocks for custom low- to high-voltage output interfaces. Aspects of reliability, device protection, and circuit design techniques are addressed. Y1 - 1993 SN - 0-7803-0826-3 U6 - https://doi.org/10.1109/CICC.1993.590766 SP - 24.6.1 EP - 24.6.4 ER - TY - JOUR A1 - Schubert, Martin J. W. A1 - Höfflinger, Bernd A1 - Zingg, René P. T1 - A One-Dimensional Analytical Model for the Dual-Gate-Controlled Thin-Film SOI MOSFET JF - IEEE Electron Device Letters N2 - A one-dimensional analytical model for dual-gate-controlled SOI MOSFETs is presented and applied to a stacked p-channel MOSFET fabricated by epitaxial lateral overgrowth (ELO). The authors found and modeled a nonlinear dependence of front-gate threshold voltage on back-gate voltage if threshold is defined by a constant current instead of a constant silicon-surface potential. It is demonstrated by comparison of subthreshold slopes that surface potentials are not pinned to the onset of strong inversion or accumulation. Accurate one-dimensional modeling is a necessity for device characterization and a precondition for general SOI models for circuit simulation.< > Y1 - 1991 U6 - https://doi.org/10.1109/55.116927 VL - 12 IS - 9 SP - 489 EP - 491 ER - TY - PAT A1 - Declerq, Michel A1 - Schubert, Martin J. W. T1 - Circuit Intermédiaire entre un Circuit Logique à Basse-Tension et un Etage de Sortie à Haute-Tension Réalisés dans une Technologie CMOS Standard N2 - La présente invention concerne un circuit intermédiaire entre un circuit logique a basse tension et un étage de sortie à haute tension réalisés dans une technologie CMOS standard. L'étage de sortie (20) comporte deux transistors respectivement à canal N et à canal P, réalisés selon une technologie CMOS standard. Le circuit intermédiaire comporte un translateur de niveau de tension (21) couplé entre un circuit logique d'entrée SL et ledit étage de sortie (20). Ce translateur de niveau de tension (21) est réalisé selon une technologie CMOS standard et est constitué d'au moins deux blocs de base identiques formant des miroirs de tension interconnectés de façon croisée. Ce circuit est utilisé pour commander des transducteurs, des écrans plasma et des actionneurs électromécaniques. Y1 - 1992 ER -