TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen A1 - Racek, Stanislav T1 - Comparison of Enhanced Markov Models and Discrete Event Simulation – for evaluation of probabilistic Faults in safety-critical real-time task sets T2 - Proceedings of EUROMICRO DSD 2014 - 17th Euromicro Conference on Digital System Design N2 - In this paper we present simulation and model based approaches for evaluating and validating the temporal and safety relevant properties of software intensive safety-critical real-time embedded systems. A high level reliability model of a safe task execution is described by a continuous-time Markov process, enhanced by the modeling of execution times. It is shown that the behavior - regarding real-time and safety metrics - of this theoretical model can be transferred into an abstract system timing model, which then can be analyzed by a discrete event simulation approach. The verification of the discrete event simulation by Markov models offers the possibility of a holistic approach for reliability analysis combined with schedulability analysis of complex safety-critical multicore real-time systems by the discrete event simulation. KW - Model KW - Stochastic simulation KW - reliability analysis KW - safe software processing KW - real-time operating system KW - multicore scheduling KW - discrete event simulation KW - fault injection Y1 - 2014 U6 - https://doi.org/10.1109/DSD.2014.42 SP - 591 EP - 598 ER - TY - GEN A1 - Krämer, Stefan T1 - Effects of Arbitrary Hardware Faults on Multicore Scheduling in Safety-critical Applications – Evaluation by enhanced Markov models and discrete event simulation T2 - 2014 PESW - The 2nd Prague Embedded Systems Workshop, June 2014 Y1 - 2014 UR - https://pesw.fit.cvut.cz/2014/presentations/pesw2014_Kramer.pdf ER - TY - CHAP A1 - Oklapi, Erna A1 - Deubzer, Michael A1 - Schmidhuber, Stefan A1 - Lalo, Erjola A1 - Mottok, Jürgen T1 - Optimization of Real-Time Multicore Systems Reached by a Genetic Algorithm Approach for Runnable Sequencing T2 - 2014 International Conference on Applied Electronics, Pilsen, Czech Republic N2 - The deployment of complex real-time systems with everyday increasing demands and possibilities, is a challenging task for engineers when performance and efficiency have to be maximized while cost have to be minimized at the same time. For already designed systems it became necessary to perform different modifications in order to find optimal software architecture configuration by respecting all timing constraints which are essential when speaking of real-time systems. In this work, we present a model-based approach of optimizing the execution sequence of runnables within tasks in order to reduce the system's reaction times by improving the overall signal flow duration. Hereby, a genetic optimization algorithm is used to create and evaluate multiple solutions for the runnable sequencing problem. We conclude by demonstration the efficiency of the presented approach with experimental results. KW - runnable sequencing KW - embedded real-time systems KW - genetic algorithms KW - multi-core KW - optimization Y1 - 2014 U6 - https://doi.org/10.1109/AE.2014.7011709 SP - 233 EP - 238 ER - TY - CHAP A1 - Oklapi, Erna A1 - Deubzer, Michael A1 - Schmidhuber, Stefan A1 - Mottok, Jürgen T1 - Verification of an Evolutionary Optimization Algorithm for Runnable Sequencing Problem T2 - 4th Applied Research Conference, 5th July 2014, Ingolstadt Y1 - 2014 ER - TY - CHAP A1 - Soska, Alexander A1 - Schumm, Michael A1 - Joseph, Saskia A1 - Reschke, Michael A1 - Mottok, Jürgen A1 - Niemetz, Michael A1 - Schroll-Decker, Irmgard T1 - Comparison of Frontal Lecture and Workshop Learning Arrangements in a Software Engineering Education Project T2 - 2014 IEEE Global Engineering Education Conference (EDUCON), Istanbul, Turkey N2 - The increase in complexity of software and its creation over the last decades requires an increase in the quality of the education of software engineering professionals. The number of Universities which answer this call by replacing or extending lectures with simulated software projects is constantly rising. However, the question how to best transfer new technological knowledge needed to be successful within this projects to the students remains open. Therefore this paper will present a comparison between the classical frontal lecture and a modern workshop learning arrangement used within these projects. By the use of workshops not only the knowledge transfer but also the acquisition of personal and social competences will be facilitated. Furthermore positive experiences with workshops at university level will support life-long learning. Y1 - 2014 U6 - https://doi.org/10.1109/EDUCON.2014.6826162 SP - 653 EP - 658 ER - TY - CHAP A1 - Soska, Alexander A1 - Mottok, Jürgen T1 - A New Conceptual Contribution for Serious Games in Academic Software Engineering Education T2 - European Conference on Software Engineering Education 2014 (ECSEE), 27 and 28 November 2014 in Seeon Monastery N2 - Nowadays, the popularity and field of application of serious games grows steadily. This educational method offers attractive pportunities for teaching and training by combining playful elements with learning content. By using game mechanics, thinking and technique, theoretical subject matters are treated in a fun and engaging way. Thereby, serious games utilize our intrinsic motivation to discover the surroundings in a playful manner. Embedded in educational settings, the goal is to mediate academic and non-academic knowledge to the students. Especially in the field of software engineering it is important to have skills which go beyond pure technical knowledge. Yet, the use of serious games is still a manageable amount. With this paper, we give a contribution to the theoretical design and development of serious games based on playful learning method and its relation to research-based learning in universal context. In addi- tion we analyze the existing serious games in software engineering and present our thoughts about planning our own. Y1 - 2014 UR - https://www.researchgate.net/publication/277266392_A_New_Conceptual_Contribution_for_Serious_Games_in_Academic_Software_Engineering_Education SN - 978-3-8440-3067-9 SP - 241 EP - 254 PB - Shaker CY - Aachen ER - TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen T1 - Simulationsbasierte Reliability-Analyse – Einflüsse von zufälligen Fehlern auf das Echtzeit-Scheduling T2 - Tagungsband 5th Embedded Software Engineering Kongress, 3. bis 7. Dezember 2012, Sindelfingen Y1 - 2012 SP - 613 EP - 622 ER - TY - CHAP A1 - Schumm, Michael A1 - Joseph, Saskia A1 - Mottok, Jürgen A1 - Niemetz, Michael A1 - Schroll-Decker, Irmgard T1 - Lernarrangements im software engineering und deren evaluation – neue konzepte für hochschule und lebenslanges Lernen T2 - Tagungsband 5th Embedded Software Engineering Kongress, 3. bis 7. Dezember 2012, Sindelfingen Y1 - 2012 ER - TY - CHAP A1 - Braun, Jürgen A1 - Mottok, Jürgen A1 - Miedl, Christian A1 - Geyer, Dirk A1 - Minas, Mark T1 - Increasing the reliability of single and multicore systems with software rejuvenation and coded processing T2 - Automotive Safety & Security 2012, Sicherheit und Zuverlässigkeit für automobile Informationstechnik, 14.-15. Nov. 2012, Karlsruhe N2 - The safety of electric vehicles has the highest priority because it helps contribute to customer confidence and thereby ensures further growth of the electromobility market. Therefore in series production redundant hardware concepts like dual core microcontrollers running in lock-step-mode are used to reach ASIL D safety requirements given from the ISO 26262. Coded processing is capable of reducing redundancy in hardware by adding diverse redundancy in software, e.g. by specific coding of data and instructions. A system with two coded processing channels is considered. One channel is active and one is in cold standby. When the active channel fails, the service is switched from the active channel to the standby channel. It is imaginable that the two channels with implemented coded processing are running with time redundancy on a single core or on a multi core system where for example different ASIL levels are partitioned on different cores. In this paper a redundant concept based on coded processing and software rejuvenation will be taken into account. Y1 - 2012 UR - https://dl.gi.de/handle/20.500.12116/17555 SP - 163 EP - 178 ER - TY - CHAP A1 - Alfranseder, Martin A1 - Mottok, Jürgen T1 - Kommunikationsmechanismen für sicherheitskritische multi-core Echtzeit-Systeme T2 - 5th Automotive Summerschool, Regensburg, September 2012 Y1 - 2012 ER - TY - CHAP A1 - Miedl, Christian A1 - Braun, Jürgen T1 - Powertrain and electric system design of a 800-volt all-electric car T2 - European Conference on Nanoelectronics and Embedded Systems for Electric Mobility, eMotion in Smart Cities, 24.-28. September, 2012, Bologna, Italy Y1 - 2012 ER - TY - CHAP A1 - Braun, Jürgen A1 - Mottok, Jürgen A1 - Miedl, Christian A1 - Geyer, Dirk A1 - Minas, Mark T1 - Capability of single hardware channel for automotive safety applications according to ISO 26262 T2 - 2012 International Conference on Applied Electronics (AE 2012), Pilsen, Czech Republic, 5 - 7 September 2012 Y1 - 2012 SN - 978-80-261-0038-6 SP - 41 EP - 45 ER - TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen A1 - Racek, Stanislav T1 - Reliability analysis of real-time scheduling by means of stochastic simulation T2 - 2012 International Conference on Applied Electronics (AE 2012), Pilsen, Czech Republic, 5 - 7 September 2012 N2 - We present a simulation-based approach to reliability analysis combined with a schedulability analysis of software intensive embedded real-time systems. In such a system not only does the software execution have to be hardened against soft errors, e.g., by means of coded processing or diverse execution, but also the real-time requirements have still to be met in the presence of such error to guarantee a safe operation of the system. For that reason, the influence regarding the real-time characteristics of a given sporadic error with a certain error rate is analyzed by means of a Monte Carlo simulation. Different safety design patterns are introduced and compared. Furthermore, the impact on the schedulability of an embedded system is discussed. Y1 - 2012 SP - 151 EP - 156 ER - TY - CHAP A1 - Mottok, Jürgen A1 - Alfranseder, Martin A1 - Schmidhuber, Stefan A1 - Mucha, Matthias A1 - Sailer, Andreas ED - Teodorescu, Horia-Nicolai ED - Kirschenbaum, Alan ED - Cojocaru, Svetlana ED - Bruderlein, Claude T1 - How to improve the reactiveness and efficiency of embedded multicore systems by use of probabilistic simulation and optimization techniques T2 - Improving Disaster Resilience and Mitigation - New Means and Tools. NATO Science for Peace and Security Series C: Environmental Security N2 - Safe and reliable multi-core technology becomes more and more important in the field of embedded systems. Today’s and future embedded systems require increasing performance while being more energy efficient. Moreover, the functional safety for these embedded systems has to be improved or developed completely new. In this chapter, we first address the challenges of embedded multi-core real-time systems. To raise the resilience of such systems we use the deadlock-free synchronization model of Block et al. (A flexible real-time locking protocol for multiprocessors. 2012 IEEE international conference on embedded and real-time computing systems and applications, vol 0, pp 47–56, 2007). The metric mean Normalized Blocking Time (mNBT) is hereby used to measure the timing effects of the blocking behavior of strongly interacting tasks. In a second step, we present a model-based approach to map the tasks of an embedded real-time system to the cores of a multi-core processor. Moreover, we derive an execution time model from runtime measurements of software functions. This information is then used to perform precise probabilistic simulations of different task-to-core mappings and evaluate them with regard to task response times, inter-task blocking overhead and load distribution. Subsequently, we integrate the probabilistic simulation within an optimization technique to systematically improve the task-to-core mapping. We conclude with a case-study, where we demonstrate the effectiveness of the presented approach by optimizing the task-to-core mapping of a practical automotive powertrain system. KW - Embed System KW - Functional Safety KW - Arrival Curve KW - Task Allocation Problem KW - Deadline Violation Y1 - 2014 U6 - https://doi.org/10.1007/978-94-017-9136-6_16 SP - 253 EP - 268 PB - Springer CY - Dodrecht ER - TY - CHAP A1 - Krämer, Stefan A1 - Simsek, Erol A1 - Braun, Jürgen A1 - Deubzer, Michael A1 - Stingl, Armin A1 - Hobelsberger, Martin A1 - Mottok, Jürgen T1 - Mut zu Fehlern, um die Qualität zu steigern – Fault-Injection zur Steigerung der Zuverlässigkeit T2 - Tagungsband, 6th Embedded Software Engineering, Kongress 2013, 2. bis 6. Dezember 2013, Sindelfingen Y1 - 2013 SN - 978-3-8343-2408-5 SP - 577 EP - 585 ER - TY - CHAP A1 - Sailer, Andreas A1 - Schmidhuber, Stefan A1 - Deubzer, Michael A1 - Mottok, Jürgen T1 - Amalthea – Plattform für kontinuierliche, modellbasierte Entwicklung T2 - Tagungsband, 6th Embedded Software Engineering, Kongress 2013, 2. bis 6. Dezember 2013, Sindelfingen Y1 - 2013 SP - 538 EP - 544 ER - TY - CHAP A1 - Raab, Peter A1 - Racek, Stanislav A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Data Flow Analysis of Software Executed by Unreliable Hardware T2 - 16th Euromicro Conference on Digital System Design, Los Alamitos, CA, USA N2 - The data flow is a crucial part of software execution in recent applications. It depends on the concrete implementation of the realized algorithm and it influences the correctness of a result in case of hardware faults during the calculation. In logical circuits, like arithmetic operations in a processor system, arbitrary faults become a more tremendous aspect in future. With modern manufacturing processes, the probability of such faults will increase and the result of a software's data flow will be more vulnerable. This paper shows a principle evaluation method for the reliability of a software's data flow with arbitrary soft errors also with the concept of fault compensation. This evaluation is discussed by means of a simple example based on an addition. KW - data flow KW - error probability KW - fault compensation KW - reliability analysis KW - software-implemented-hardwarefault-tolerance (SIHFT) Y1 - 2013 U6 - https://doi.org/10.1109/DSD.2013.35 SP - 243 EP - 249 ER - TY - CHAP A1 - Braun, Jürgen A1 - Mottok, Jürgen T1 - Fail-Safe and Fail-Operational Systems safeguarded with Coded Processing T2 - 2013 IEEE EUROCON - International Conference on Computer as a Tool, Zagreb, Croatia, July 1-4, 2013 N2 - Safety has the highest priority because it helps contribute to customer confidence and thereby ensures further growth of the new markets, like electromobility. Therefore in series production redundant hardware concepts like dual core microcontrollers running in lock-step-mode are used to reach for example ASIL D safety requirements given from the ISO 26262. Coded processing is capable of reducing redundancy in hardware by adding diverse redundancy in software, e.g. by specific coding of data and instructions. A system with two coded processing channels is considered. Both channels are active. When one channel fails, the service can be continued with the other channel. It is imaginable that the two channels with implemented coded processing are running with time redundancy on a single core or on a multi core system where for example different ASIL levels are partitioned on different cores. In this paper a redundancy concept based on coded processing will be taken into account. The improvement of the Mean Time To Failure by safeguarding the system with coded processing will be computed for fail-safe as well as for fail-operational systems. The use of the coded processing approach in safeguarding failsafe systems is proved. KW - fail-safe KW - fail-operational KW - fault-tolerant KW - failure probability KW - coded processing KW - Safely Embedded Software KW - SES KW - safety measure KW - ISO 26262 KW - electromobility KW - Mean Time To Failure KW - MTTF KW - reliability KW - diversity Y1 - 2013 SN - 978-1-4673-2231-7 U6 - https://doi.org/10.1109/EUROCON.2013.6625234 SP - 1878 EP - 1885 ER - TY - CHAP A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Error Model and the Reliability of Arithmetic Operations T2 - 2013 IEEE EUROCON - International Conference on Computer as a Tool, Zagreb, Croatia, July 1-4, 2013 N2 - Error detecting and correcting codes are widely used in data transmission, storage systems and also for data processing. In logical circuits like arithmetic operations, arbitrary faults can cause errors in the result. However in safety critical applications, it is important to avoid those errors which would lead to system failures. Several approaches are known to protect the result of operations during software processing. In the same way like transmission systems, coded processing uses codes for fault detection. But in contrast to transmission systems, there is no adequate channel model available which makes it possible to evaluate the residue error probability of an arithmetic operation in an analytical way. This paper tries to close the gap of arithmetic error models by the development of a model for an ordinary addition in a computer system. Thus, the reliability of an addition's result can be analytically evaluated. KW - addition KW - channel model KW - coded processing KW - fault simulation KW - Markov model KW - residue error probability Y1 - 2013 U6 - https://doi.org/10.1109/EUROCON.2013.6625047 SP - 630 EP - 637 ER - TY - CHAP A1 - Alfranseder, Martin A1 - Krapf, Tobias A1 - Mottok, Jürgen A1 - Siemers, Christian T1 - Synchronisationsverfahren in embedded Multicoresystemen T2 - Tagungsband, 6th Embedded Software Engineering, Kongress 2013, 2. bis 6. Dezembern 2013, Sindelfingen Y1 - 2013 PB - Vogel Business Media CY - Würzburg ER -