<?xml version="1.0" encoding="utf-8"?>
<export-example>
  <doc>
    <id>1283</id>
    <completedYear/>
    <publishedYear>2017</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Pattern oriented card game development: SOFTTY - A card game for academic learning of software testing</title>
    <abstract language="eng">One of the biggest problems of educational games is the adequate integration of learning content into the game environment. Thereby the main challenge is to create a balance between gameplay and learning objectives and the correct transfer of learning principles into the game design. A useful approach is to identify game components and their specific learning constraints and the relationship between each other. By mapping learning elements to Game Design Pattern, we elaborate fundamentals for the concrete game design, focusing on card games. A shared description and an understanding of how the game design aligns with learning content facilitates the development of high quality educational games. A short illustration of our further developed implementation summarizes our experiences and shows an exemplary realization.</abstract>
    <parentTitle language="eng">IEEE Global Engineering Education Conference (EDUCON), 25-28 April 2017, Athens, Greece</parentTitle>
    <identifier type="doi">10.1109/EDUCON.2017.7942996</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <enrichment key="BegutachtungStatus">peer-reviewed</enrichment>
    <author>Alexander Soska</author>
    <author>Jürgen Mottok</author>
    <author>Christian Wolff</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1286</id>
    <completedYear/>
    <publishedYear>2017</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>1</pageFirst>
    <pageLast>9</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">A Survey of Fault Tolerance Approaches at Different Architecture Levels</title>
    <abstract language="eng">In the recent years the development trends for computing platforms moved to multicore systems. Associated with this trend, feature sizes decreased with each new hardware generation and consequently led to a rise of transient and permanent error frequency in memory and CPUs. In this context, researchers presented several approaches which exploit the inherent redundancy of multicore platforms to provide fault tolerance. We present a discussion of fault tolerance approaches based on redundancy at different levels of architecture regarding theirsphereofreplication,performanceaswellaserrordetection and recovery capability.</abstract>
    <parentTitle language="eng">30th International Conference on Architecture of Computing Systems, ARCS 2017, 3-6 April 2017, Vienna, Austria</parentTitle>
    <identifier type="url">https://ieeexplore.ieee.org/document/7948561</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <author>Lukas Osinski</author>
    <author>Tobias Langer</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1281</id>
    <completedYear/>
    <publishedYear>2017</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>1631</pageFirst>
    <pageLast>1635</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Work in Progress: Teaching-Obstacles in Higher Software Engineering Education</title>
    <abstract language="eng">Software Engineering is very abstract and complex by nature. Teaching Software Engineering in higher education is therefore still a big challenge. Although we implemented inductive teaching and learning methods in our courses for several years, we do not have a panacea. This paper aims to identify the remaining teaching obstacles in our Software Engineering courses with regard to the concrete teaching content. We present first ideas on how to overcome these teaching obstacles by the application of Augmented and/or Virtual Reality techniques with regard to the identified obstacles.</abstract>
    <parentTitle language="eng">8th IEEE Global Engineering Education Conference (EDUCON 2017), Athens, Greece</parentTitle>
    <identifier type="doi">10.1109/EDUCON.2017.7943067</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <author>Rebecca Reuter</author>
    <author>Magdalena Beslmeisl</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16314">Lebenswissenschaften und Ethik</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1279</id>
    <completedYear/>
    <publishedYear>2017</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>10259</pageFirst>
    <pageLast>10267</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Towards a Definition and Identification of Learning Obstacles in Higher Software Engineering Education</title>
    <parentTitle language="eng">EDULEARN17 Proceedings, 9th International Conference on Education and New Learning Technologies, 3-5 July, 2017, Barcelona, Spain</parentTitle>
    <identifier type="issn">2340-1117</identifier>
    <identifier type="isbn">978-84-697-3777-4</identifier>
    <identifier type="doi">10.21125/edulearn.2017.0943</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <author>Rebecca Reuter</author>
    <author>Florian Hauser</author>
    <author>Carolin Gold-Veerkamp</author>
    <author>Jürgen Mottok</author>
    <author>Jörg Abke</author>
    <subject>
      <language>deu</language>
      <type>swd</type>
      <value>Hochschuldidaktik</value>
    </subject>
    <subject>
      <language>deu</language>
      <type>swd</type>
      <value>Software Engineering</value>
    </subject>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16314">Lebenswissenschaften und Ethik</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1277</id>
    <completedYear/>
    <publishedYear>2017</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Detecting errors in program flow diagrams: Comparing novices and advanced programmers</title>
    <parentTitle language="eng">EARLI Biennial Conference 2017, 17th European Association for Research on Learning and Instruction, 29 August - 2 September, 2017 - University of Tampere, Finland</parentTitle>
    <enrichment key="opus.source">publish</enrichment>
    <author>Markus Nivala</author>
    <author>Florian Hauser</author>
    <author>Helen Jossberger</author>
    <author>Markus Reiß</author>
    <author>Jürgen Mottok</author>
    <author>Hans Gruber</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16315">Information und Kommunikation</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1280</id>
    <completedYear/>
    <publishedYear>2017</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>460</pageFirst>
    <pageLast>467</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">A Two-Sided Approach of Applying Software Engineering Perspectives in Higher Education</title>
    <parentTitle language="eng">Teaching and Learning in a Digital World, ICL 2017, Proceedings of the 20th International Conference on Interactive Collaborative Learning - Volume 1</parentTitle>
    <enrichment key="opus.source">publish</enrichment>
    <author>Rebecca Reuter</author>
    <author>Martina Kuhn</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16314">Lebenswissenschaften und Ethik</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1284</id>
    <completedYear/>
    <publishedYear>2017</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>report</type>
    <publisherName/>
    <publisherPlace>Regensburg</publisherPlace>
    <creatingCorporation>Ostbayerische Technische Hochschule Regensburg</creatingCorporation>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">An Experimental Card Game for Software Testing</title>
    <parentTitle language="eng">Forschungsbericht 2017 der Ostbayersichen Technischen Hochschule Regensburg</parentTitle>
    <identifier type="url">https://doi.org/10.35096/othr/pub-1383</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <author>Alexander Soska</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16315">Information und Kommunikation</collection>
  </doc>
  <doc>
    <id>1290</id>
    <completedYear/>
    <publishedYear>2018</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>900</pageFirst>
    <pageLast>908</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">A ‘laboratory’ as an approach to foster writing skills at software engineering studies learning software engineering is easier when writing courses are directly dpplied to lecture’s content and the problems and examples enrolled in</title>
    <abstract language="eng">Writing, with no doubt, is besides reading a core competency which allows us to "exploit" knowledge in general. It also makes possible the exploration of software engineering's core issues. Especially within this context it is necessary to master the reading of complex texts as well as to be able to write in an appropriate academic expression. With regard to studies in software engineering this seems to be obvious, but in fact the opposite is the reality. Therefore measures to improve these skills seemed to be necessarily applied. At the Ostbayerische Technische Hochschule (OTH, University of Applied Sciences, Regensburg) a new format, the so called c*lab, was installed during the winter semester 2017. This was a course which followed the principle of "Writing Across the Curriculum" (WAC). Organized parallel to a lecture of learning how to program the language C, and addressing students of the first semester, the course was a complete voluntary offer in addition to the general standard courses and lectures of the faculty. Students who participated not only reflected on C and its principles, nor only on writing as a self purpose, but they also learned to express technical thoughts and ideas by the use of didactic methods. The idea to transfer also basic LTeX concepts to write a paper based on the IEEE bare_conf.tex-template were also planned. The course followed the idea of student's-centred learning. This paper presents the main structure, goals, and means of the c*lab, and the theory behind. It also embeds the course within the horizon of experiences of teaching writing skills at the Laboratory for Safe and Secure Systems (LaS 3 ) at the faculty of electronic and information engineering at the OTH Regensburg. First experiences have shown that participants increase writing skills and their idea of the importance of writing.</abstract>
    <parentTitle language="eng">2018 IEEE Global Engineering Education Conference, EDUCON 2018, Santa Cruz de Teneriffe, Spanien</parentTitle>
    <identifier type="doi">10.1109/EDUCON.2018.8363326</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <enrichment key="BegutachtungStatus">peer-reviewed</enrichment>
    <author>Matthias Kampmann</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16314">Lebenswissenschaften und Ethik</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1295</id>
    <completedYear/>
    <publishedYear>2019</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>1</pageFirst>
    <pageLast>7</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Control Flow Errors: A Discussion of Different Injection Strategies</title>
    <abstract language="eng">Among the available dependability assessment techniques, fault injection (FI) is widely adopted and strongly recommended by safety standards for the validation that functional and technical safety mechanisms are implemented correctly and effectively. The main challenge in fault injection assessments is the increasing complexity of system-on-chips as well as the increasing size of memory, which leads to enormous efforts to test every possible fault introduced to the system. Therefore, a number of publicly available fault injection frameworks utilize fault space pruning techniques to reduce the overall fault space and consequently the overall experiment duration. Most of the fault space pruning techniques mainly discuss the reduction of the number of data errors which have to be injected into registers and memory locations. However, control flow errors represent a further domain of possible errors on the application level. Usually for the evaluation of effectiveness of fault tolerance mechanisms against data errors, a single fault assumption at microarchitectural level (e.g. bit-flips) is assumed. In most cases, this assumption is equivalently applied to the program counter to investigate possible control flow errors. Due to this approach, the error space is consciously or unconsciously reduced to the possible erroneous jump targets that can be reached by a specific set of bit-flips in the program counter at a specified time during the program execution. This approach is considered valid regarding the corresponding fault assumption, but leads to negative effects on the significance of the injection and the resulting effectiveness of the tested fault tolerance mechanism. In this paper, we discuss different strategies for the analysis and injection of control flow errors and the resulting differences by considering the single fault assumption at microarchitectural and application level.</abstract>
    <parentTitle language="eng">32nd International Conference on Architecture of Computing Systems, ARCS Workshop 2019, 20-21 May 2019, Copenhagen, Denmark</parentTitle>
    <identifier type="url">http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&amp;arnumber=8836207&amp;isnumber=8836190</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <enrichment key="BegutachtungStatus">peer-reviewed</enrichment>
    <licence>Keine Lizenz - Es gilt das deutsche Urheberrecht: § 53 UrhG</licence>
    <author>Lukas Osinski</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16315">Information und Kommunikation</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1292</id>
    <completedYear/>
    <publishedYear>2019</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>1</pageFirst>
    <pageLast>8</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">On Solving Task Allocation and Schedule Generation for Time-Triggered LET Systems using Constraint Programming</title>
    <abstract language="eng">The amount of safety-critical embedded systems in automotive development is heavily growing. Ensuring their reliability not only increases the complexity of functions but also requires determinism at design and execution time, which is considerably challenging to fulfill and verify for multi-core processors. The Logical Execution Time (LET) is recently recognized in automotive industry as an approach for ensuring deterministic functional behavior. However, to decrease the manual design effort and time for deploying such complex systems to multi-core platforms and for ensuring their strict timing and safety requirements, automatic solutions are needed. This work presents a solution for allocating tasks to multi-core processors and generating a time-triggered schedule for embedded systems considering safety, timing, and LET semantics. The approach we propose solves both challenges by defining them as a Constraint Satisfaction Problem (CSP). To examine our CSP formulation, we use MiniZinc, which is a solver-independent constraint modeling language that can employ a variety of solvers. In a case study, we explore optimizations of an industrial system that are enabled by scheduling and task allocation design decisions. Further, the performance of the proposed solutions is evaluated based on large set of synthetically generated system models.</abstract>
    <parentTitle language="eng">32nd International Conference on Architecture of Computing Systems, ARCS Workshop 2019, 20-21 May 2019, Copenhagen, Denmark</parentTitle>
    <identifier type="url">https://ieeexplore.ieee.org/abstract/document/8836201</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <enrichment key="BegutachtungStatus">peer-reviewed</enrichment>
    <licence>Keine Lizenz - Es gilt das deutsche Urheberrecht: § 53 UrhG</licence>
    <author>Erjola Lalo</author>
    <author>Raphael Weber</author>
    <author>Andreas Sailer</author>
    <author>Jürgen Mottok</author>
    <author>Christian Siemers</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1289</id>
    <completedYear/>
    <publishedYear>2018</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Parallel Active Object Pattern</title>
    <abstract language="eng">With parallel applications becoming more and more popular even in real-time systems, the demand for safe and easyto- use software libraries and frameworks for parallel and concurrent computations is growing immensely. These frameworks usually provide an implementation for different sets of software patterns. A very well known software pattern for concurrency is the Active Object pattern, that allows various threads to have synchronized access to an object in question. This paper presents the Parallel Active Object pattern, which extends the common Active Object pattern to support the use of objects, whose computations are profoundly enhanced by a parallel execution. Furthermore, a C++ software framework is introduced, which implements the Parallel Active Object pattern and thus provides the possibility of using task or data parallel patterns, for example Map, Reduce and Divide-and-Conquer, on the active object's calculations. The proposed framework is evaluated against two other popular libraries, namely OpenMP and Intel Threading Building Blocks. Through utilization of the C++11 standard and template classes a simple user interface is provided, which abstracts the distribution of workloads among the worker threads. By making use of the C++ Standard Template Library the framework can easily be ported to embedded systems and by extending the pattern through real-time capabilities, which ensure a timely and reliable execution of the method requests, the intention of providing the framework for time critical environments is also targeted in the future.</abstract>
    <parentTitle language="eng">31th International Conference on Architecture of Computing Systems, ARCS Workshop 2018,9-12 April 2018, Braunschweig, Germany</parentTitle>
    <identifier type="isbn">978-3-8007-4559-3</identifier>
    <identifier type="url">https://ieeexplore.ieee.org/document/8385426</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <author>Michael Schmid</author>
    <author>Tobias Langer</author>
    <author>Lukas Osinski</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1293</id>
    <completedYear/>
    <publishedYear>2019</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>1</pageFirst>
    <pageLast>8</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName>IEEE</publisherName>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Synchronization Techniques for Parallel Redundant Execution of Applications</title>
    <abstract language="eng">In fault tolerant systems, applications are replicated and executed to enable error detection and recovery. If one replica application fails, another is able to take its place and provide the correct results. This concept can benefit from parallel execution on separate execution units. The rise of multicore platforms supports the development of parallel software, by providing the adequate hardware. However, this raises challenges regarding the synchronization of the redundant strings of execution. Replica determinism means that given the same input, identical programs provide the same output. To ensure replica determinism, requirements regarding the synchronization can be split in two domains: data and time. This paper examines the state of the art of synchronization techniques for parallel replicated execution in the context of fault tolerant systems. We analyze the requirements regarding synchronization within the time and data domain and compare different concepts of hardware (multicore, multiprocessor and multi-PCB) and software (processes, threads).</abstract>
    <parentTitle language="eng">32nd International Conference on Architecture of Computing Systems, ARCS Workshop 2019, 20-21 May 2019, Copenhagen, Denmark</parentTitle>
    <identifier type="url">http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&amp;arnumber=8836209&amp;isnumber=8836190</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <enrichment key="BegutachtungStatus">peer-reviewed</enrichment>
    <licence>Keine Lizenz - Es gilt das deutsche Urheberrecht: § 53 UrhG</licence>
    <author>Christian Nagengast</author>
    <author>Lukas Osinski</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16315">Information und Kommunikation</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1299</id>
    <completedYear/>
    <publishedYear>2018</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">A Multicore Fault Tolerance Approach Based on Coded Processing</title>
    <abstract language="eng">Development trends for computing platforms moved from increasing the frequency of a single processor to increasing the parallelism with multiple cores on the same die. Multiple cores have strong potential to support cost-efficient fault tolerance due to their inherent spatial redundancy. This work makes a step towards software-only fault tolerance in the presence of permanent and transient hardware faults. Our approach utilizes software-based spatial triple modular redundancy and coded processing on a shared memory multi-core controller. We evaluate our approach on an Infineon AURIX TriBoard TC277 and provide experimental evidence for error resistance by fault injection campaigns with an iSystem iC5000 On-chip Analyzer.</abstract>
    <parentTitle language="eng">Embedded Real-Time Software and Systems Conference (ERST²), Jan 2018, Toulouse/France</parentTitle>
    <identifier type="url">https://hal.archives-ouvertes.fr/hal-02156233</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <licence>Keine Lizenz - Es gilt das deutsche Urheberrecht: § 53 UrhG</licence>
    <author>Lukas Osinski</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="oaweg" number="">Diamond Open Access - OA-Veröffentlichung ohne Publikationskosten (Sponsoring)</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1297</id>
    <completedYear/>
    <publishedYear>2019</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>571</pageFirst>
    <pageLast>578</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName>Pro BUSINESS</publisherName>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Use of Static Analysis and Coding Guidelines in embedded Systems Software</title>
    <parentTitle language="eng">1st Applied Research Conference, ARC 2019, 8 July 2019, Regensburg</parentTitle>
    <identifier type="isbn">978-3-96409-182-6</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <author>Jürgen Mottok</author>
    <author>Marcus Reichenberger</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1301</id>
    <completedYear/>
    <publishedYear>2018</publishedYear>
    <thesisYearAccepted/>
    <language>deu</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="deu">Das FORMUS³IC Forschungsvorhaben im Verbund – Vom Stand der Technik zu neuen Entwicklungen</title>
    <parentTitle language="deu">Embedded Software Engineering Kongress (ESE 2018), 3.-7.12.2018, Sindelfingen, Tagungsband</parentTitle>
    <enrichment key="opus.source">publish</enrichment>
    <author>Lukas Osinski</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1306</id>
    <completedYear/>
    <publishedYear>2018</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>457</pageFirst>
    <pageLast>466</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Towards the construction of a questionnaire for the identification of learning obstacles</title>
    <abstract language="eng">This paper deals with the identification of learning ob-stacles using the questionnaire method. Therefore, two iterations were proceeded: The first one was part of a survey that was carried out at four lo-cations at universities of applied sciences. We asked students about obstructive facts in general providing items for five learning ob-stacle dimensions that were set up before; emotional/motivational, epistemological/cognitive,  didactical,  resource-related  and  meta-cognitive learning obstacle dimensions.  After the general part, we asked them to answer the same question, but in relation to the  – in their opinion – most difficult learning content. With this question, we aim to get indications regarding to epistemological obstacles. In a second step, we used the “Motivated Strategies for Learning Questionnaire”, which was developed by Pintrich [1] as a basis to develop  a  questionnaire  that  extracts  learning  obstacles.  In  its original version, the “Motivated Strategies for Learning Question-naire” was intended to measure students’ learning strategies, but, as  the  obstacle  dimensions  were  partly  derived  from  learning strategy  classification,  we  chose  this  already  validated  question-naire  [2].  Within  this  iteration,  we  could  confirm  a  five-factor structure of the questionnaire that could be mapped to the five be-fore set learning obstacle dimensions.</abstract>
    <parentTitle language="eng">2018 IEEE Global Engineering Education Conference (EDUCON 2018), 17-20 April, 2018, Santa Cruz de Tenerife, Spain</parentTitle>
    <identifier type="doi">10.1109/EDUCON.2018.8363266</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <author>Rebecca Reuter</author>
    <author>Florian Hauser</author>
    <author>Carolin Gold-Veerkamp</author>
    <author>Theresa Stark</author>
    <author>Juliane Kis</author>
    <author>Jürgen Mottok</author>
    <author>Jörg Abke</author>
    <author>Dany Meyer</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16314">Lebenswissenschaften und Ethik</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1305</id>
    <completedYear/>
    <publishedYear>2018</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>109</pageFirst>
    <pageLast>117</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Research competence: Modification of a questionnaire to measure research competence at universities of applied sciences</title>
    <abstract language="eng">This paper deals with the validation and modification of the German questionnaire "F-Komp". In its original version, it was intended to measure university students' research competences. In the beginning of this study, there were only a few tools available which were reliable. For the purposes of this study, they were not suitable. At the same time, there was no validated version of the F-Komp available, which made the whole validation process for further usage necessary. This questionnaire is based on a structure, which consist of different skills and knowledge and is focused on measuring research competence in general. The validation and modification of the F-Komp is therefore the aim of our contribution as well as a revised version of the questionnaire. We proceeded an explorative factor and a reliability analysis to do a general evaluation of the tool. Some modifications were done in the questionnaire to make it more suitable to the requirements of technical oriented universities of applied sciences [5]. Our revised version is slightly longer and contains several items to gather data about the participants demographics. The modified questionnaire is based on a more appropriate factor structure. This structure is more practically oriented and pays attention to ethical issues. In future cases, this questionnaire will be used in research oriented courses to measure students' progress in acquiring the knowledge and methods which are necessary to perform as a scientist in different research areas.</abstract>
    <parentTitle language="eng">IEEE Global Engineering Education Conference (EDUCON), 17-20 April 2018, Santa Cruz de Tenerife, Spain</parentTitle>
    <identifier type="doi">10.1109/EDUCON.2018.8363216</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <enrichment key="BegutachtungStatus">peer-reviewed</enrichment>
    <author>Florian Hauser</author>
    <author>Rebecca Reuter</author>
    <author>Hans Gruber</author>
    <author>Jürgen Mottok</author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>research oriented teaching</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>research competence</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>competence model</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>modification of a questionnaire</value>
    </subject>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16314">Lebenswissenschaften und Ethik</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1302</id>
    <completedYear/>
    <publishedYear>2019</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>56</pageFirst>
    <pageLast>67</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName>Springer</publisherName>
    <publisherPlace>Cham</publisherPlace>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Asynchronous Critical Sections in Real-Time Multiprocessor Systems</title>
    <abstract language="eng">Sharing data across multiple tasks in multiprocessor systems has intensively been studied in the past decades. Various synchronization protocols, the most well-known being the Priority Inheritance Protocol or the Priority Ceiling Protocol, have been established and analyzed so that blocking times of tasks waiting to access a shared resource can be upper bounded. To the best of our knowledge, all of these protocols share one commonality: Tasks that want to enter a critical section, that is already being executed by another task, immediately get blocked. In this paper, we introduce the Asynchronous Priority Ceiling Protocol (A-PCP), which makes use of aperiodic servers to execute the critical sections asynchronously, while the calling task can continue its work on non-critical section code. For this protocol, we provide a worst-case response time analysis of the asynchronous computations, as well as necessary and sufficient conditions for a feasibility analysis of a set of periodic tasks using the proposed synchronization model on a system that preemptively schedules the tasks under the rate-monotonic priority assignment.</abstract>
    <parentTitle language="eng">Architecture of Computing Systems - ARCS 2019, 32nd International Conference, Copenhagen, Denmark, May 20-23, 2019, Proceedings</parentTitle>
    <identifier type="doi">10.1007/978-3-030-18656-2_5</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <enrichment key="OtherSeries">Lecture Notes in Computer Science ; 11479</enrichment>
    <enrichment key="BegutachtungStatus">begutachtet</enrichment>
    <author>Michael Schmid</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1314</id>
    <completedYear/>
    <publishedYear>2018</publishedYear>
    <thesisYearAccepted/>
    <language>deu</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>book</type>
    <publisherName>dpunkt.Verlag</publisherName>
    <publisherPlace>Heidelberg</publisherPlace>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="deu">Modellbasierte Softwareentwicklung für eingebettete Systeme verstehen und anwenden</title>
    <abstract language="deu">Die Beherrschung von Komplexität ist eine der größten Engineering-Herausforderungen des 21. Jahrhunderts. Themen wie das „Internet der Dinge“ (IoT) und „Industrie 4.0“ beschleunigen diesen Trend. Die modellgetriebene Entwicklung leistet einen entscheidenden Beitrag, um diesen Herausforderungen erfolgreich begegnen zu können.&#13;
&#13;
Die Autoren geben einen fundierten Einstieg und praxisorientierten Überblick über die Modellierung von Software für eingebettete Systeme von den Anforderungen über die Architektur bis zum Design, der Codegenerierung und dem Testen. Für jede Phase werden Paradigmen,&#13;
Methoden, Techniken und Werkzeuge beschrieben und ihre praktische Anwendung in den Vordergrund gestellt. Darüber hinaus wird auf die Integration von Werkzeugen, funktionale Sicherheit und Metamodellierung eingegangen sowie die Einführung eines modellbasierten Ansatzes in einer Organisation und die Notwendigkeit zum lebenslangen Lernen erläutert.&#13;
&#13;
Der Leser erfährt in diesem Buch, wie ein modellbasiertes Vorgehen nutzbringend in der Praxis für die Softwareentwicklung eingesetzt wird. Das Vorgehen wird unabhängig von Modellierungswerkzeugen vorgestellt. Zahlreiche Beispiele – exemplarisch auch auf Basis konkreter Werkzeuge – helfen bei der praktischen Umsetzung.</abstract>
    <identifier type="isbn">978-3-86490-524-7</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <author>Tim Weilkiens</author>
    <author>Alexander Huwaldt</author>
    <author>Jürgen Mottok</author>
    <author>Stephan Roth</author>
    <author>Andreas Willert</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>1303</id>
    <completedYear/>
    <publishedYear>2019</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-07</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Benchmarking Software Implementations of 1st Round Candidates of the NIST LWC Project on Microcontrollers</title>
    <abstract language="eng">This paper introduces a custom framework for benchmarking software implementations from the National Institute of Standards and Technology (NIST)  Lightweight  Cryptography  (LWC)  project  on  embedded  devices. We present the design and core functions of the framework and apply it to various NIST LWC authenticated encryption with associated data (AEAD) ciphers. Altogether, we evaluate the speed of 213 submitted algorithm vari-ants on four different microcontroller units (MCUs), including 32 bit ARM and 8 bit AVR architectures.  To allow a more meaningful comparison, we also conduct code size tests on all four boards and RAM utilization tests on one test platform.</abstract>
    <parentTitle language="eng">3rd Lightweight Cryptography Workshop at NIST, Gaithersburg, USA</parentTitle>
    <identifier type="url">https://csrc.nist.gov/CSRC/media/Events/lightweight-cryptography-workshop-2019/documents/papers/benchmarking-software-implementations-lwc2019.pdf</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <author>Sebastian Renner</author>
    <author>Enrico Pozzobon</author>
    <author>Jürgen Mottok</author>
    <author>Rudolf Hackenberg</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="institutes" number="FakIM">Fakultät Informatik und Mathematik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="institutes" number="">Labor Informationssicherheit und Complience (ISC)</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
</export-example>
