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  <doc>
    <id>7508</id>
    <completedYear/>
    <publishedYear>2024</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
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    <title language="eng">Problems and New Approaches for Crypto-Agility in Operational Technology</title>
    <abstract language="eng">In recent years, cybersecurity has also become relevant for Operational Technology (OT). Critical systems like industrial automation systems or transportation systems are faced with new threats, and therefore require the implementation of thorough security measures. Regulations further mandate the deployment and regular verification of these security measures. However, OT systems differ from well-known systems of classic Information Technology (IT), such as mission times spanning decades, infrequent updates only during on-site maintenance, or diverse devices with varying support for security measures. The growing field of crypto-agility examines approaches to integrate security measures in an agile and flexible way, making updates easier and, therefore, encouraging a more frequent deployment of them. This paper contributes to this research field in the context of secure communication in two ways. We first examine the current state of crypto-agility by providing an overview of existing measures for OT systems. Then, we propose a new architecture concept with different deployment approaches to integrate security measures in a crypto-agile way. Based on a security library with a generic interface and a flexible proxy application, our architecture is capable of securing both new OT systems and existing ones via retrofit.</abstract>
    <parentTitle language="eng">12th European Congress Embedded Real Time Systems (ERTS 2024), 11-12 June 2024, Toulouse, France</parentTitle>
    <identifier type="url">https://www.researchgate.net/publication/383709526_Problems_and_New_Approaches_for_Crypto-Agility_in_Operational_Technology</identifier>
    <enrichment key="opus.import.date">2024-09-08T09:13:13+00:00</enrichment>
    <enrichment key="opus.source">sword</enrichment>
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    <licence>Keine Lizenz - Es gilt das deutsche Urheberrecht: § 53 UrhG</licence>
    <author>Tobias Frauenschläger</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
  </doc>
  <doc>
    <id>7502</id>
    <completedYear/>
    <publishedYear>2024</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>26</pageFirst>
    <pageLast>35</pageLast>
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    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
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    <title language="eng">Implementation of a Bump-in-the-Wire Security Gateway</title>
    <abstract language="eng">In the face of escalating cyber threats, the integration of Operational Technology (OT) with Information Technology (IT) systems presents heightened vulnerabilities to critical infrastructures. This paper focuses on the need for cybersecurity, showcasing the design and implementation of a security gateway to achieve bump-in-the-wire security between two units to be protected (assets). For that, each asset is assigned one security module that safeguards its communication paths. To ease bump-in-the-wire capability, the communication between the asset and the security-gateway must be stateless and operate on OSI layer 2. This is necessary to safeguard the whole communication bandwidth, regardless of the used protocols. For this objective, Linux-based packet sockets are used. An encrypted tunnel is established between two security gateways using the Datagram Transport Layer Security (DTLS) protocol. The results show that the implemented solution is capable of securing the asset’s network traffic without the need of any modifications.</abstract>
    <parentTitle language="eng">Proceedings of the 12th Prague Embedded Systems Workshop, June 27 - 29, 2024, Horoměřice, Czech Republic</parentTitle>
    <identifier type="isbn">978-80-01-07303-2</identifier>
    <identifier type="url">https://pesw.fit.cvut.cz/2024/PESW_2024.pdf</identifier>
    <enrichment key="opus.import.date">2024-09-08T09:07:35+00:00</enrichment>
    <enrichment key="opus.source">sword</enrichment>
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    <licence>Keine Lizenz - Es gilt das deutsche Urheberrecht: § 53 UrhG</licence>
    <author>Philipp Schwind</author>
    <author>Tobias Frauenschläger</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
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  <doc>
    <id>7505</id>
    <completedYear/>
    <publishedYear>2024</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>18</pageFirst>
    <pageLast>27</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName>Hochschule Landshut</publisherName>
    <publisherPlace>Landshut</publisherPlace>
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    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>--</completedDate>
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    <title language="eng">Integration and Evaluation of Different FPGA based Hardware Accelerators for the AES Algorithm in the TLS Protocol to be Used in Critical Automation Systems</title>
    <abstract language="eng">This thesis addresses the challenges of hardware-assisted cryptography in the context of automation systems in critical infrastructures. While hardware accelerators enhance cryptographic calculations in both performance and security, their permanence poses issues in adapting to evolving security concerns. To overcome this problem, we integrated and evaluated a hardware accelerator for the AES algorithm on an FPGA within a TLS application, comparing its performance with other accelerators. Employing a hybrid FPGA-CPU processor system, this setup achieves over 800 Mbit/s data rates, showcasing a more than 27 times acceleration in TLS transmissions compared to purely software-based solutions. The FPGA's flexibility and upgradability therefore make it an ideal platform for critical infrastructure, ensuring longevity and superior acceleration in TLS data transfers.</abstract>
    <parentTitle language="deu">4. Symposium Elektronik und Systemintegration, Tagungsband: Symposium am 17. April 2024 Hochschule Landshut</parentTitle>
    <identifier type="url">https://www.haw-landshut.de/static/ITZ/Bilder/Cluster_MST/ESI_Symposium/ESI_2024/Tagungsband/1B2_Frauenschlaeger_OTH-R_TB-ESI2024_s18-27.pdf</identifier>
    <identifier type="isbn">978-3-9818439-9-6</identifier>
    <enrichment key="opus.import.date">2024-09-08T09:13:13+00:00</enrichment>
    <enrichment key="opus.source">sword</enrichment>
    <enrichment key="opus.import.user">importuser</enrichment>
    <licence>Keine Lizenz - Es gilt das deutsche Urheberrecht: § 53 UrhG</licence>
    <author>Luca Horn</author>
    <author>Tobias Frauenschläger</author>
    <author>Jürgen Mottok</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othforschungsschwerpunkt" number="16311">Digitalisierung</collection>
    <collection role="institutes" number="">Laboratory for Safe and Secure Systems (LAS3)</collection>
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</export-example>
