<?xml version="1.0" encoding="utf-8"?>
<export-example>
  <doc>
    <id>1169</id>
    <completedYear/>
    <publishedYear>1993</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>24.6.1</pageFirst>
    <pageLast>24.6.4</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-06</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Design and Optimization of High-Voltage CMOS Devices Compatible wih a Standard 5V CMOS Technology</title>
    <abstract language="eng">High-voltage n- and p-MOSFETs fully compatible with a standard 5 V CMOS technology have been designed, optimized, and fabricated. No process changes are required. By modifying the logical equations generating one of the physical masks from the design masks, a p-type buffer region for the high-voltage p-MOS was easily implemented. This modification does not affect the low-voltage part of the circuits. These high-voltage devices have been used successfully as output drivers in semicustom arrays, and as building blocks for custom low- to high-voltage output interfaces. Aspects of reliability, device protection, and circuit design techniques are addressed.</abstract>
    <parentTitle language="eng">Proceedings of IEEE Custom Integrated Circuits Conference, May 9-12 1993, San Diego, CA, USA</parentTitle>
    <identifier type="isbn">0-7803-0826-3</identifier>
    <identifier type="doi">10.1109/CICC.1993.590766</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <author>Michel Declerq</author>
    <author>F. Clément</author>
    <author>Martin J. W. Schubert</author>
    <author>Adnan Harb</author>
    <author>Michel Dutoit</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othpublikationsherkunft" number="">Externe Publikationen</collection>
    <collection role="othforschungsschwerpunkt" number="16316">Produktion und Systeme</collection>
    <collection role="institutes" number="">Labor Elektronik</collection>
  </doc>
  <doc>
    <id>1168</id>
    <completedYear/>
    <publishedYear>1992</publishedYear>
    <thesisYearAccepted/>
    <language>fra</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>patent</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation>Institut National de la Propriété Industrielle, Paris</contributingCorporation>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-06</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="fra">Circuit Intermédiaire entre un Circuit Logique à Basse-Tension et un Etage de Sortie à Haute-Tension Réalisés dans une Technologie CMOS Standard</title>
    <abstract language="fra">La présente invention concerne un circuit intermédiaire entre un circuit logique a basse tension et un étage de sortie à haute tension réalisés dans une technologie CMOS standard. L'étage de sortie (20) comporte deux transistors respectivement à canal N et à canal P, réalisés selon une technologie CMOS standard. Le circuit intermédiaire comporte un translateur de niveau de tension (21) couplé entre un circuit logique d'entrée SL et ledit étage de sortie (20). Ce translateur de niveau de tension (21) est réalisé selon une technologie CMOS standard et est constitué d'au moins deux blocs de base identiques formant des miroirs de tension interconnectés de façon croisée. Ce circuit est utilisé pour commander des transducteurs, des écrans plasma et des actionneurs électromécaniques.</abstract>
    <enrichment key="PatentNr">92 06030</enrichment>
    <enrichment key="PatentLand">Frankreich</enrichment>
    <enrichment key="PatentYear">1992</enrichment>
    <enrichment key="PatentDate">05.05.1992</enrichment>
    <enrichment key="PatentZugriff">weltweit</enrichment>
    <enrichment key="opus.source">publish</enrichment>
    <author>Michel Declerq</author>
    <author>Martin J. W. Schubert</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othpublikationsherkunft" number="">Externe Publikationen</collection>
    <collection role="othforschungsschwerpunkt" number="16316">Produktion und Systeme</collection>
    <collection role="institutes" number="">Labor Elektronik</collection>
  </doc>
  <doc>
    <id>1170</id>
    <completedYear/>
    <publishedYear>1993</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>162</pageFirst>
    <pageLast>163</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-06</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">5V-to-75V CMOS Output Interfaces</title>
    <abstract language="eng">A family of CMOS low- to high-voltage output interface circuits based on a standard, unmodified low-voltage CMOS technology is described. Using only thin-oxide high-voltage (HV) devices with reduced V/sub GS/ (gate-to-source voltage) swing, it makes use of level-shift techniques to meet the constraints on the gate control signals. These static circuits permit the full output voltage swing of V/sub DDH/, while keeping the V/sub GS/ swing of the output devices within the safety limits, including during HV supply transients. Using a standard 2- mu m n-well CMOS technology, reliable, reproducible V/sub DS/ breakdown voltages as high as 120 V and 80 V have been obtained for HV-nMOS and HV-pMOS devices, respectively.&lt; &gt;</abstract>
    <parentTitle language="eng">Proceedings of the1993 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 24-26 1993, San Francisco, CA, USA</parentTitle>
    <identifier type="doi">10.1109/ISSCC.1993.280014</identifier>
    <enrichment key="opus.source">publish</enrichment>
    <author>Michel Declerq</author>
    <author>Martin J. W. Schubert</author>
    <author>F. Clément</author>
    <collection role="institutes" number="FakEI">Fakultät Elektro- und Informationstechnik</collection>
    <collection role="othpublikationsherkunft" number="">Externe Publikationen</collection>
    <collection role="othforschungsschwerpunkt" number="16316">Produktion und Systeme</collection>
    <collection role="institutes" number="">Labor Elektronik</collection>
  </doc>
</export-example>
