@inproceedings{DeclerqClementSchubertetal., author = {Declerq, Michel and Cl{\´e}ment, F. and Schubert, Martin J. W. and Harb, Adnan and Dutoit, Michel}, title = {Design and Optimization of High-Voltage CMOS Devices Compatible wih a Standard 5V CMOS Technology}, series = {Proceedings of IEEE Custom Integrated Circuits Conference, May 9-12 1993, San Diego, CA, USA}, booktitle = {Proceedings of IEEE Custom Integrated Circuits Conference, May 9-12 1993, San Diego, CA, USA}, isbn = {0-7803-0826-3}, doi = {10.1109/CICC.1993.590766}, pages = {24.6.1 -- 24.6.4}, abstract = {High-voltage n- and p-MOSFETs fully compatible with a standard 5 V CMOS technology have been designed, optimized, and fabricated. No process changes are required. By modifying the logical equations generating one of the physical masks from the design masks, a p-type buffer region for the high-voltage p-MOS was easily implemented. This modification does not affect the low-voltage part of the circuits. These high-voltage devices have been used successfully as output drivers in semicustom arrays, and as building blocks for custom low- to high-voltage output interfaces. Aspects of reliability, device protection, and circuit design techniques are addressed.}, language = {en} } @inproceedings{DeclerqSchubertClement, author = {Declerq, Michel and Schubert, Martin J. W. and Cl{\´e}ment, F.}, title = {5V-to-75V CMOS Output Interfaces}, series = {Proceedings of the1993 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 24-26 1993, San Francisco, CA, USA}, booktitle = {Proceedings of the1993 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 24-26 1993, San Francisco, CA, USA}, doi = {10.1109/ISSCC.1993.280014}, pages = {162 -- 163}, abstract = {A family of CMOS low- to high-voltage output interface circuits based on a standard, unmodified low-voltage CMOS technology is described. Using only thin-oxide high-voltage (HV) devices with reduced V/sub GS/ (gate-to-source voltage) swing, it makes use of level-shift techniques to meet the constraints on the gate control signals. These static circuits permit the full output voltage swing of V/sub DDH/, while keeping the V/sub GS/ swing of the output devices within the safety limits, including during HV supply transients. Using a standard 2- mu m n-well CMOS technology, reliable, reproducible V/sub DS/ breakdown voltages as high as 120 V and 80 V have been obtained for HV-nMOS and HV-pMOS devices, respectively.< >}, language = {en} } @misc{DeclerqSchubert, author = {Declerq, Michel and Schubert, Martin J. W.}, title = {Circuit Interm{\´e}diaire entre un Circuit Logique {\`a} Basse-Tension et un Etage de Sortie {\`a} Haute-Tension R{\´e}alis{\´e}s dans une Technologie CMOS Standard}, abstract = {La pr{\´e}sente invention concerne un circuit interm{\´e}diaire entre un circuit logique a basse tension et un {\´e}tage de sortie {\`a} haute tension r{\´e}alis{\´e}s dans une technologie CMOS standard. L'{\´e}tage de sortie (20) comporte deux transistors respectivement {\`a} canal N et {\`a} canal P, r{\´e}alis{\´e}s selon une technologie CMOS standard. Le circuit interm{\´e}diaire comporte un translateur de niveau de tension (21) coupl{\´e} entre un circuit logique d'entr{\´e}e SL et ledit {\´e}tage de sortie (20). Ce translateur de niveau de tension (21) est r{\´e}alis{\´e} selon une technologie CMOS standard et est constitu{\´e} d'au moins deux blocs de base identiques formant des miroirs de tension interconnect{\´e}s de fa{\c{c}}on crois{\´e}e. Ce circuit est utilis{\´e} pour commander des transducteurs, des {\´e}crans plasma et des actionneurs {\´e}lectrom{\´e}caniques.}, language = {fr} }