@inproceedings{SailerDeubzerLuettgenetal., author = {Sailer, Andreas and Deubzer, Michael and L{\"u}ttgen, Gerald and Mottok, J{\"u}rgen}, title = {CoreTAna: A Trace Analyzer for Reverse Engineering Real-Time Software}, series = {IEEE 23rd International Conference on Software Analysis, Evolution, and Reengineering (SANER), March 14 to March 18 2016, Suita, Osaka, Japan}, booktitle = {IEEE 23rd International Conference on Software Analysis, Evolution, and Reengineering (SANER), March 14 to March 18 2016, Suita, Osaka, Japan}, doi = {10.1109/SANER.2016.36}, abstract = {With the availability of the AUTOSAR standard, model-driven methodologies are becoming established in theautomotive domain. However, the process of creating models ofexisting system components is often difficult and time consuming, especially when legacy code has to be re-used or informationabout the exact timing behavior is needed. In order to tackle thisreverse engineering problem, we present CoreTAna, a novel toolthat derives an AUTOSAR compliant model of a real-time systemfrom a dynamic analysis of its trace recordings. This paper givesan overview of CoreTAna's current features and discusses itsbenefits for reverse engineering.}, language = {en} } @inproceedings{LaloWeberSaileretal., author = {Lalo, Erjola and Weber, Raphael and Sailer, Andreas and Mottok, J{\"u}rgen and Siemers, Christian}, title = {On Solving Task Allocation and Schedule Generation for Time-Triggered LET Systems using Constraint Programming}, series = {32nd International Conference on Architecture of Computing Systems, ARCS Workshop 2019, 20-21 May 2019, Copenhagen, Denmark}, booktitle = {32nd International Conference on Architecture of Computing Systems, ARCS Workshop 2019, 20-21 May 2019, Copenhagen, Denmark}, pages = {1 -- 8}, abstract = {The amount of safety-critical embedded systems in automotive development is heavily growing. Ensuring their reliability not only increases the complexity of functions but also requires determinism at design and execution time, which is considerably challenging to fulfill and verify for multi-core processors. The Logical Execution Time (LET) is recently recognized in automotive industry as an approach for ensuring deterministic functional behavior. However, to decrease the manual design effort and time for deploying such complex systems to multi-core platforms and for ensuring their strict timing and safety requirements, automatic solutions are needed. This work presents a solution for allocating tasks to multi-core processors and generating a time-triggered schedule for embedded systems considering safety, timing, and LET semantics. The approach we propose solves both challenges by defining them as a Constraint Satisfaction Problem (CSP). To examine our CSP formulation, we use MiniZinc, which is a solver-independent constraint modeling language that can employ a variety of solvers. In a case study, we explore optimizations of an industrial system that are enabled by scheduling and task allocation design decisions. Further, the performance of the proposed solutions is evaluated based on large set of synthetically generated system models.}, language = {en} } @inproceedings{LaloSailerMottoketal., author = {Lalo, Erjola and Sailer, Andreas and Mottok, J{\"u}rgen and Siemers, Christian}, title = {Overhead-Aware Schedule Synthesis for Logical Execution Time (LET) in Automotive Systems}, series = {2022 IEEE 35th International System-on-Chip Conference (SOCC): 05-08 September 2022, Belfast, United Kingdom}, booktitle = {2022 IEEE 35th International System-on-Chip Conference (SOCC): 05-08 September 2022, Belfast, United Kingdom}, publisher = {IEEE}, isbn = {978-1-6654-5985-3}, doi = {10.1109/SOCC56010.2022.9908103}, pages = {1 -- 6}, abstract = {The Logical Execution Time (LET) has recently been integrated in multi-core automotive systems to ensure timing and dataflow determinism. Although buffering mechanisms are introduced to incorporate LET semantics, they do not guarantee that tasks are executed within their LET frames. In fact, LET and buffering semantics are violated if scheduling is not designed to execute all tasks within their LET frames and in a specific order. In this paper, we describe a scheduling synthesis technique for Fixed-Priority Scheduling (FPS) to achieve resource-efficient execution of LET systems. The proposed approach considers LET semantics, scheduling overheads, and delays caused by operating system operations and provides the possibility to optimize the schedule with respect to aspects like scheduling overheads. Our performance and feasibility evaluation shows that the proposed algorithm provides results in a reasonable amount of time for models of complex industrial applications. Thus, the integration of the proposed algorithm into an automated process is of high benefit to accelerate the development of vehicle applications.}, language = {en} }