@inproceedings{LaloSailerMottoketal., author = {Lalo, Erjola and Sailer, Andreas and Mottok, J{\"u}rgen and Siemers, Christian}, title = {Overhead-Aware Schedule Synthesis for Logical Execution Time (LET) in Automotive Systems}, series = {2022 IEEE 35th International System-on-Chip Conference (SOCC): 05-08 September 2022, Belfast, United Kingdom}, booktitle = {2022 IEEE 35th International System-on-Chip Conference (SOCC): 05-08 September 2022, Belfast, United Kingdom}, publisher = {IEEE}, isbn = {978-1-6654-5985-3}, doi = {10.1109/SOCC56010.2022.9908103}, pages = {1 -- 6}, abstract = {The Logical Execution Time (LET) has recently been integrated in multi-core automotive systems to ensure timing and dataflow determinism. Although buffering mechanisms are introduced to incorporate LET semantics, they do not guarantee that tasks are executed within their LET frames. In fact, LET and buffering semantics are violated if scheduling is not designed to execute all tasks within their LET frames and in a specific order. In this paper, we describe a scheduling synthesis technique for Fixed-Priority Scheduling (FPS) to achieve resource-efficient execution of LET systems. The proposed approach considers LET semantics, scheduling overheads, and delays caused by operating system operations and provides the possibility to optimize the schedule with respect to aspects like scheduling overheads. Our performance and feasibility evaluation shows that the proposed algorithm provides results in a reasonable amount of time for models of complex industrial applications. Thus, the integration of the proposed algorithm into an automated process is of high benefit to accelerate the development of vehicle applications.}, language = {en} } @inproceedings{SailerSchmidhuberDeubzeretal., author = {Sailer, Andreas and Schmidhuber, Stefan and Deubzer, Michael and Alfranseder, Martin and Mucha, Matthias and Mottok, J{\"u}rgen}, title = {Optimizing the task allocation step for multi-core processors within autosar}, series = {2013 International Conference on Applied Electronics, IEEE, Pilsen, Czech Republic}, booktitle = {2013 International Conference on Applied Electronics, IEEE, Pilsen, Czech Republic}, abstract = {We present a model-based optimization approach for the task allocation problem in embedded multi-core systems. The information therefore is obtained from a system description in AUTOSAR and runtime measurements of the runnables in hardware traces. Based on this an initial software partitioning of runnables to tasks is created. We then use a genetic algorithm to create and evaluate solutions to the task allocation problem. Each solution is hereby evaluated using a discrete event-based simulation, which allows the evaluation with regard to real-time properties, resource consumption and data-communication overhead. The significance of our approach is then shown in a case-study. There, we optimize the task allocation of an embedded system, whose complexity is comparable to that of an actual system, on a multi-core processor. Finally, the results of the optimization are transferred to an ECU Configuration Description to enable further development in compliance with the AUTOSAR methodology.}, language = {en} } @inproceedings{AlfransederMuchaSchmidhuberetal., author = {Alfranseder, Martin and Mucha, Matthias and Schmidhuber, Stefan and Sailer, Andreas and Niemetz, Michael and Mottok, J{\"u}rgen}, title = {A modified synchronization model for dead-lock free concurrent execution of strongly interacting task sets in embedded systems}, series = {2013 International Conference on Applied Electronics (AE 2013), IEEE, 10-12 September 2013, Pilsen, Czech Republic}, volume = {18}, booktitle = {2013 International Conference on Applied Electronics (AE 2013), IEEE, 10-12 September 2013, Pilsen, Czech Republic}, pages = {13 -- 18}, abstract = {Global scheduling algorithms are very promising for application in embedded real-time systems using multi-core controllers. In this paper we want to make a first step forward to apply such scheduling methods on real existing systems. Especially a new resource model is necessary to avoid deadlocks, as this goal can not be achieved by using the standard OSEK Priority Ceiling Protocol when shared global resources are in use. We also introduce the new metric mean Normalized Blocking Time in order to be able to compare locking mechanisms according to the timing effects of their blocking behavior. Finally we give a simulative application example of the new metric by the use of two different kinds of semaphore models and an example task set typical for existing embedded real-time systems in the automotive powertrain environment.}, language = {en} } @misc{AlfransederSchmidhuberMuchaetal., author = {Alfranseder, Martin and Schmidhuber, Stefan and Mucha, Matthias and Sailer, Andreas and Mottok, J{\"u}rgen}, title = {How to improve the reactiveness and efficiency of embedded multicore systems by use of probabilistic simulation and optimization techniques: A case study}, series = {Advanced Research Workshop: Improving Disaster Resilience and Mitigation - New Means and Tools, Trends, Iasi}, journal = {Advanced Research Workshop: Improving Disaster Resilience and Mitigation - New Means and Tools, Trends, Iasi}, language = {en} } @inproceedings{SailerSchmidhuberDeubzeretal., author = {Sailer, Andreas and Schmidhuber, Stefan and Deubzer, Michael and Mottok, J{\"u}rgen}, title = {Amalthea - Plattform f{\"u}r kontinuierliche, modellbasierte Entwicklung}, series = {Tagungsband, 6th Embedded Software Engineering, Kongress 2013, 2. bis 6. Dezember 2013, Sindelfingen}, booktitle = {Tagungsband, 6th Embedded Software Engineering, Kongress 2013, 2. bis 6. Dezember 2013, Sindelfingen}, pages = {538 -- 544}, language = {de} } @inproceedings{SailerDeubzerLuettgenetal., author = {Sailer, Andreas and Deubzer, Michael and L{\"u}ttgen, Gerald and Mottok, J{\"u}rgen}, title = {CoreTAna: A Trace Analyzer for Reverse Engineering Real-Time Software}, series = {IEEE 23rd International Conference on Software Analysis, Evolution, and Reengineering (SANER), March 14 to March 18 2016, Suita, Osaka, Japan}, booktitle = {IEEE 23rd International Conference on Software Analysis, Evolution, and Reengineering (SANER), March 14 to March 18 2016, Suita, Osaka, Japan}, doi = {10.1109/SANER.2016.36}, abstract = {With the availability of the AUTOSAR standard, model-driven methodologies are becoming established in theautomotive domain. However, the process of creating models ofexisting system components is often difficult and time consuming, especially when legacy code has to be re-used or informationabout the exact timing behavior is needed. In order to tackle thisreverse engineering problem, we present CoreTAna, a novel toolthat derives an AUTOSAR compliant model of a real-time systemfrom a dynamic analysis of its trace recordings. This paper givesan overview of CoreTAna's current features and discusses itsbenefits for reverse engineering.}, language = {en} } @inproceedings{LaloWeberSaileretal., author = {Lalo, Erjola and Weber, Raphael and Sailer, Andreas and Mottok, J{\"u}rgen and Siemers, Christian}, title = {On Solving Task Allocation and Schedule Generation for Time-Triggered LET Systems using Constraint Programming}, series = {32nd International Conference on Architecture of Computing Systems, ARCS Workshop 2019, 20-21 May 2019, Copenhagen, Denmark}, booktitle = {32nd International Conference on Architecture of Computing Systems, ARCS Workshop 2019, 20-21 May 2019, Copenhagen, Denmark}, pages = {1 -- 8}, abstract = {The amount of safety-critical embedded systems in automotive development is heavily growing. Ensuring their reliability not only increases the complexity of functions but also requires determinism at design and execution time, which is considerably challenging to fulfill and verify for multi-core processors. The Logical Execution Time (LET) is recently recognized in automotive industry as an approach for ensuring deterministic functional behavior. However, to decrease the manual design effort and time for deploying such complex systems to multi-core platforms and for ensuring their strict timing and safety requirements, automatic solutions are needed. This work presents a solution for allocating tasks to multi-core processors and generating a time-triggered schedule for embedded systems considering safety, timing, and LET semantics. The approach we propose solves both challenges by defining them as a Constraint Satisfaction Problem (CSP). To examine our CSP formulation, we use MiniZinc, which is a solver-independent constraint modeling language that can employ a variety of solvers. In a case study, we explore optimizations of an industrial system that are enabled by scheduling and task allocation design decisions. Further, the performance of the proposed solutions is evaluated based on large set of synthetically generated system models.}, language = {en} } @incollection{MottokAlfransederSchmidhuberetal., author = {Mottok, J{\"u}rgen and Alfranseder, Martin and Schmidhuber, Stefan and Mucha, Matthias and Sailer, Andreas}, title = {How to improve the reactiveness and efficiency of embedded multicore systems by use of probabilistic simulation and optimization techniques}, series = {Improving Disaster Resilience and Mitigation - New Means and Tools. NATO Science for Peace and Security Series C: Environmental Security}, booktitle = {Improving Disaster Resilience and Mitigation - New Means and Tools. NATO Science for Peace and Security Series C: Environmental Security}, editor = {Teodorescu, Horia-Nicolai and Kirschenbaum, Alan and Cojocaru, Svetlana and Bruderlein, Claude}, publisher = {Springer}, address = {Dodrecht}, doi = {10.1007/978-94-017-9136-6_16}, pages = {253 -- 268}, abstract = {Safe and reliable multi-core technology becomes more and more important in the field of embedded systems. Today's and future embedded systems require increasing performance while being more energy efficient. Moreover, the functional safety for these embedded systems has to be improved or developed completely new. In this chapter, we first address the challenges of embedded multi-core real-time systems. To raise the resilience of such systems we use the deadlock-free synchronization model of Block et al. (A flexible real-time locking protocol for multiprocessors. 2012 IEEE international conference on embedded and real-time computing systems and applications, vol 0, pp 47-56, 2007). The metric mean Normalized Blocking Time (mNBT) is hereby used to measure the timing effects of the blocking behavior of strongly interacting tasks. In a second step, we present a model-based approach to map the tasks of an embedded real-time system to the cores of a multi-core processor. Moreover, we derive an execution time model from runtime measurements of software functions. This information is then used to perform precise probabilistic simulations of different task-to-core mappings and evaluate them with regard to task response times, inter-task blocking overhead and load distribution. Subsequently, we integrate the probabilistic simulation within an optimization technique to systematically improve the task-to-core mapping. We conclude with a case-study, where we demonstrate the effectiveness of the presented approach by optimizing the task-to-core mapping of a practical automotive powertrain system.}, language = {en} } @inproceedings{SailerSchmidhuberDeubzeretal., author = {Sailer, Andreas and Schmidhuber, Stefan and Deubzer, Michael and Hobelsberger, Martin and Mottok, J{\"u}rgen}, title = {Requirements engineering for a continuous design flow and methodology}, series = {2nd Applied Research Conference 2012 (ARC 2012) 25./26. June 2012, Nuremberg}, booktitle = {2nd Applied Research Conference 2012 (ARC 2012) 25./26. June 2012, Nuremberg}, publisher = {Shaker}, address = {Aachen}, isbn = {978-3-8440-1093-0}, pages = {76 -- 79}, language = {en} } @inproceedings{SchmidhuberSailerDeubzeretal., author = {Schmidhuber, Stefan and Sailer, Andreas and Deubzer, Michael and Hobelsberger, Martin and Mottok, J{\"u}rgen}, title = {Overview of the itea2-project amalthea}, series = {2nd Applied Research Conference 2012 (ARC 2012) 25./26. June 2012, Nuremberg}, booktitle = {2nd Applied Research Conference 2012 (ARC 2012) 25./26. June 2012, Nuremberg}, publisher = {Shaker}, address = {Aachen}, isbn = {978-3-8440-1093-0}, pages = {60 -- 62}, language = {en} } @inproceedings{MartinSailerDeubzeretal., author = {Martin, Felix and Sailer, Andreas and Deubzer, Michael and Mottok, J{\"u}rgen}, title = {Automatische Multicore-Echtzeitvalidierung - Ein Prozess f{\"u}r modellbasierte Softwareentwicklung}, series = {Tagungsband 8th Embedded Software Engineering Kongress (ESE), 30.11. - 04.12.2015, Sindelfingen}, booktitle = {Tagungsband 8th Embedded Software Engineering Kongress (ESE), 30.11. - 04.12.2015, Sindelfingen}, language = {de} } @inproceedings{MartinSailerDeubzeretal., author = {Martin, Felix and Sailer, Andreas and Deubzer, Michael and Mottok, J{\"u}rgen}, title = {Automation of a Closed Loop Model-Based Development Process}, series = {Applied Research Conference 2015 (ARC 2015), 3rd July 2015, N{\"u}rnberg}, booktitle = {Applied Research Conference 2015 (ARC 2015), 3rd July 2015, N{\"u}rnberg}, language = {en} } @inproceedings{SailerDeubzerLuettgenetal., author = {Sailer, Andreas and Deubzer, Michael and L{\"u}ttgen, Gerald and Mottok, J{\"u}rgen}, title = {Comparing Trace Recordings of Automotive Realtime Software}, series = {RTNS '17: Proceedings of the 25th International Conference on Real-Time Networks and Systems, Grenoble, France, IEEE}, booktitle = {RTNS '17: Proceedings of the 25th International Conference on Real-Time Networks and Systems, Grenoble, France, IEEE}, doi = {10.1145/3139258.3139265}, pages = {118 -- 127}, abstract = {The process of engineering models of existing real-time system components is often difficult and time consuming, especially when legacy code has to be re-used or information about the exact timing behaviour is needed. In order to tackle this reverse engineering problem, we have developed the tool CoreTAna. CoreTAna derives an AUTOSAR compliant model of a real-time system by conducting dynamic analysis using trace recordings. Motivated by the challenge of assessing the quality of reverse engineered models of real-time software, we present a novel mathematical measure for comparing trace recordings from embedded real-time systems regarding their temporal behaviour. We also introduce a benchmark framework based on this measure, for evaluating reverse engineering tools such as CoreTAna. This considers common system architectures and also includes randomly generated systems and three systems of industrial automotive projects. Finally, an industrial case study demonstrates other use cases of our measure, such as impact analysis.}, language = {en} }