@inproceedings{OoiLeeSchubertetal., author = {Ooi, Boon Yaik and Lee, Wai-Kong and Schubert, Martin J. W. and Ooi, Yu-Wei and Chin, Chee-Yang and Woo, Wing-Hon}, title = {A Flexible and Reliable Internet-of-Things Solution for Real-Time Production Tracking}, series = {IEEE Industrial Electronics and Applications Conference (IEACon): 22.11.2021 - 23.11.2021, Penang, Malaysia}, booktitle = {IEEE Industrial Electronics and Applications Conference (IEACon): 22.11.2021 - 23.11.2021, Penang, Malaysia}, publisher = {IEEE}, isbn = {978-1-7281-9253-6}, doi = {10.1109/IEACon51066.2021.9654672}, pages = {270 -- 275}, abstract = {The concept of Industrial Revolution 4.0 (IR4.0) has sparked the urgency of many manufacturers to revisit their manufacturing processes and search for opportunities to further improved their production output. Unfortunately, it is difficult to improve a process with inadequate data. Many of the SMEs in developing countries are still using manufacturing machines from the yesteryears which do not have computational and connectivity capabilities. Therefore, we developed an end-to-end Internet-of-Things (IoT) solution, which reliably tracks the production performance of manufacturing machines. This paper elaborates on the designs and the rationale behind it. As of the writing of this paper, our IoT system has been deployed in real manufacturing environment and has been running for approximately 90 days on a 24/7 basis without data lost.}, language = {en} } @article{SchubertHoefflingerZingg, author = {Schubert, Martin J. W. and H{\"o}fflinger, Bernd and Zingg, Ren{\´e} P.}, title = {An Analytical Model for Strongly Inverted and Accumulated Silicon Films}, series = {Solid-State Electronics}, volume = {33}, journal = {Solid-State Electronics}, number = {12}, publisher = {Elsevier}, doi = {10.1016/0038-1101(90)90136-3}, pages = {1553 -- 1567}, abstract = {An analytical model for the spatial distribution of potential, electric field and carrier densities is presented, assuming uniform doping density and constant quasi-Fermi potentials in the direction of modeling. Starting from the current relations a differential equation respecting two-dimensional effects is developed and solved approximately by decomposition in three regions with different preconditions: (a) flatband region, (b) constant spacecharge density and (c) strong inversion or accumulation. Inaccuracies arise mainly from violated preconditions at the interfaces between the different regions. Two-dimensional effects are respected in the analytical model of (b) only but they influence region (c) by means of boundary conditions at the interface of (b) and (c). The investigations of this paper are focused to region (c). This part of our model is identical to the model of Hauser and Littlejohn[1]. They integrated a simplified form of the semiconductor-Poisson equation twice but were restricted to one-dimensional applications and thermal equilibrium. Our derivation allows for large electric fields and current densities perpendicular to the direction of modeling. From analytical considerations confirmed by numerical experiments we suggest preference to the gradual channel condition, with x and y defined according to Fig. 1. This definition allows the potentials to vary significantly with respect to y. We found that this holds for the quasi-Fermi potentials also. Furthermore an empirical model for the maximum width of strong-inversion layers in uniformly doped silicon films is presented in eqn (46).}, language = {en} } @inproceedings{DeclerqClementSchubertetal., author = {Declerq, Michel and Cl{\´e}ment, F. and Schubert, Martin J. W. and Harb, Adnan and Dutoit, Michel}, title = {Design and Optimization of High-Voltage CMOS Devices Compatible wih a Standard 5V CMOS Technology}, series = {Proceedings of IEEE Custom Integrated Circuits Conference, May 9-12 1993, San Diego, CA, USA}, booktitle = {Proceedings of IEEE Custom Integrated Circuits Conference, May 9-12 1993, San Diego, CA, USA}, isbn = {0-7803-0826-3}, doi = {10.1109/CICC.1993.590766}, pages = {24.6.1 -- 24.6.4}, abstract = {High-voltage n- and p-MOSFETs fully compatible with a standard 5 V CMOS technology have been designed, optimized, and fabricated. No process changes are required. By modifying the logical equations generating one of the physical masks from the design masks, a p-type buffer region for the high-voltage p-MOS was easily implemented. This modification does not affect the low-voltage part of the circuits. These high-voltage devices have been used successfully as output drivers in semicustom arrays, and as building blocks for custom low- to high-voltage output interfaces. Aspects of reliability, device protection, and circuit design techniques are addressed.}, language = {en} } @misc{DeclerqSchubert, author = {Declerq, Michel and Schubert, Martin J. W.}, title = {Circuit Interm{\´e}diaire entre un Circuit Logique {\`a} Basse-Tension et un Etage de Sortie {\`a} Haute-Tension R{\´e}alis{\´e}s dans une Technologie CMOS Standard}, abstract = {La pr{\´e}sente invention concerne un circuit interm{\´e}diaire entre un circuit logique a basse tension et un {\´e}tage de sortie {\`a} haute tension r{\´e}alis{\´e}s dans une technologie CMOS standard. L'{\´e}tage de sortie (20) comporte deux transistors respectivement {\`a} canal N et {\`a} canal P, r{\´e}alis{\´e}s selon une technologie CMOS standard. Le circuit interm{\´e}diaire comporte un translateur de niveau de tension (21) coupl{\´e} entre un circuit logique d'entr{\´e}e SL et ledit {\´e}tage de sortie (20). Ce translateur de niveau de tension (21) est r{\´e}alis{\´e} selon une technologie CMOS standard et est constitu{\´e} d'au moins deux blocs de base identiques formant des miroirs de tension interconnect{\´e}s de fa{\c{c}}on crois{\´e}e. Ce circuit est utilis{\´e} pour commander des transducteurs, des {\´e}crans plasma et des actionneurs {\´e}lectrom{\´e}caniques.}, language = {fr} } @article{SchubertHoefflingerZingg, author = {Schubert, Martin J. W. and H{\"o}fflinger, Bernd and Zingg, Ren{\´e} P.}, title = {A One-Dimensional Analytical Model for the Dual-Gate-Controlled Thin-Film SOI MOSFET}, series = {IEEE Electron Device Letters}, volume = {12}, journal = {IEEE Electron Device Letters}, number = {9}, doi = {10.1109/55.116927}, pages = {489 -- 491}, abstract = {A one-dimensional analytical model for dual-gate-controlled SOI MOSFETs is presented and applied to a stacked p-channel MOSFET fabricated by epitaxial lateral overgrowth (ELO). The authors found and modeled a nonlinear dependence of front-gate threshold voltage on back-gate voltage if threshold is defined by a constant current instead of a constant silicon-surface potential. It is demonstrated by comparison of subthreshold slopes that surface potentials are not pinned to the onset of strong inversion or accumulation. Accurate one-dimensional modeling is a necessity for device characterization and a precondition for general SOI models for circuit simulation.< >}, language = {en} } @inproceedings{SchubertHoefflingerZingg, author = {Schubert, Martin J. W. and H{\"o}fflinger, Bernd and Zingg, Ren{\´e} P.}, title = {A New Analytical Charge Model for the Dual-Gate-Controlled Thin-Film SOI MOSFET}, series = {Superlattices and Microstructures}, volume = {7}, booktitle = {Superlattices and Microstructures}, number = {4}, publisher = {Elsevier}, doi = {10.1016/0749-6036(90)90218-V}, pages = {323 -- 326}, abstract = {An analytical model for dual-gate-controlled SOI MOSFETs is presented, assuming uniformly doped p-silicon films. It is restricted to electron inversion layers and depletion regions, neglecting hole densities. It allows to account for the spatial description of electronic quantities in the silicon film. Due to the non-linearities of the semiconductor equations the model parameters must be extracted iteratively. Some applications are presented to demonstrate the usefulness of the model.}, language = {en} } @inproceedings{SchubertBloedelConradietal., author = {Schubert, Martin J. W. and Bl{\"o}del, J. and Conradi, P. and Lafosse, P. and Nebel, W. and Neusser, S. and Ryba, M. and Schr{\"o}der, D.}, title = {Extending EDIF for Technology Data}, series = {EDIF World Conference, 1989, San Jose, CA, USA, 11.-14. September}, booktitle = {EDIF World Conference, 1989, San Jose, CA, USA, 11.-14. September}, language = {en} } @phdthesis{Schubert, author = {Schubert, Martin J. W.}, title = {Eindimensionale Modellierung von SOI MOSFETs}, address = {Hamburg}, language = {de} } @inproceedings{Schubert, author = {Schubert, Martin J. W.}, title = {Mixed-Signal Event-Driven Simulation of a Phase-Locked Loop}, series = {IEEE/VIUF International Workshops on Behavioral Modeling and Simulation (BMAS'99), October 4-6 1999, Orlando, Florida, USA}, booktitle = {IEEE/VIUF International Workshops on Behavioral Modeling and Simulation (BMAS'99), October 4-6 1999, Orlando, Florida, USA}, abstract = {The mixed-signal event-driven (MixED) simulationalgorithm using standard VHDL is capable of modelinga number of analog and mixed-signal problems in digital circuits, e.g. RCL networks representing pads or wires, charge pumps, dynamic logic, voltage-controlledoscillators, phase-locked loops, etc. Important featuresare single-kernel simulation as well as rapid A/D andD/A interfacing. This paper demonstrates the simulation of a phase-locked loop (PLL), which is one of the most interesting applications of the MixED method. Many digital designs contain a PLL as only mixed-signal building block. The MixED method allows to simulate such designs with standard VHDL.}, language = {en} } @inproceedings{DeclerqSchubertClement, author = {Declerq, Michel and Schubert, Martin J. W. and Cl{\´e}ment, F.}, title = {5V-to-75V CMOS Output Interfaces}, series = {Proceedings of the1993 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 24-26 1993, San Francisco, CA, USA}, booktitle = {Proceedings of the1993 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 24-26 1993, San Francisco, CA, USA}, doi = {10.1109/ISSCC.1993.280014}, pages = {162 -- 163}, abstract = {A family of CMOS low- to high-voltage output interface circuits based on a standard, unmodified low-voltage CMOS technology is described. Using only thin-oxide high-voltage (HV) devices with reduced V/sub GS/ (gate-to-source voltage) swing, it makes use of level-shift techniques to meet the constraints on the gate control signals. These static circuits permit the full output voltage swing of V/sub DDH/, while keeping the V/sub GS/ swing of the output devices within the safety limits, including during HV supply transients. Using a standard 2- mu m n-well CMOS technology, reliable, reproducible V/sub DS/ breakdown voltages as high as 120 V and 80 V have been obtained for HV-nMOS and HV-pMOS devices, respectively.< >}, language = {en} }