Graph theoretical algorithms for index reduction in circuit simulation
Please always quote using this URN:urn:nbn:de:0296-matheon-2543
- The numerical simulation of very large scale integrated circuits is an important tool in the development of new industrial circuits. This topic has received increasing attention within the last years. The main problem in circuit simulation is that the model equations lead to differential algebraic equations (DAEs). One known property of circuit DAEs is that they may have an index larger than one, i.e., they may contain socalled hidden constraints. The increased index has numerous disadvantages on the numerical treatment of circuit DAEs. The determination of these hidden constraints can be done investigating the circuit topology. Until now, this information has only been used for the consistent initialization of the circuit equations. A recent approach has been to reduce the index of the circuit DAE in order to improve their numerical behaviour. This paper will give graph theoretical methods that lead to constraints in a favorable formulation. Furthermore, the index reduction via minimal extension will be performed for circuit DAEs, using these constraints.
| Author: | Simone Bächle, Falk Ebert |
|---|---|
| URN: | urn:nbn:de:0296-matheon-2543 |
| Referee: | Caren Tischendorf |
| Document Type: | Preprint, Research Center Matheon |
| Language: | English |
| Date of first Publication: | 2005/05/13 |
| Release Date: | 2005/05/13 |
| Preprint Number: | 245 |

