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Embedding power semiconductor devices into printed circuit boards (PCB) provides several benefits compared to conventional packaging technologies. Integrating the semiconductor dies into the circuit board reduces the converter size. This results in short current loops, enabling low interconnection resistances and parasitic inductances. Both contribute to a higher system-level efficiency, as conduction and switching losses are reduced. Moreover, the use of thick Cu substrates allows efficient heat removal, due to a low thermal resistance. Therefore, PCB embedding has received a lot of attention in the power electronics community for more than a decade. This article aims to provide a comprehensive review of the scientific literature on the topic ranging from basic fabrication technology over module or system-level demonstrators for electrical and thermal testing to reliability studies. Performance indicators, such as the commutation loop inductance Lσ, the chip area independent thermal resistance Rth × Achip, allow a comparison of different approaches and benchmarking with conventional power modules. Several publications report stray inductances below 1 nH and chip area independent thermal resistances in the range of 20…30 mm²K/W.
PCB embedding is an attractive packaging technology for highly integrated future power systems. Electrical and thermal benefits and limitations are well understood, but only few publications focus on reliability. Here we are addressing high-humidity high temperature reverse bias (H3TRB) tests, which are performed to gain deeper understanding of the limitations of this technology. Cu filament growth is observed on both, PCB embedded samples and silicone potted reference samples. These filaments may form a conductive path and lead to an increased leakage current in blocking mode. Electrochemical corrosion of the Cu-plated guard ring is identified as root cause.
This paper presents a novel approach to embed power semiconductor devices into a printed circuit board. Here, IGBTs and diodes with reinforced top side chip contact are used in an IGBT half bridge with 25 A / 1200 V rating. Thermal simulations highlight the improved thermal impedance caused by the reinforced top contact and the benefits of the insulated copper substrate compared to a commercial DBC-based reference module.
The fabrication process is discussed in detail and preliminary test results are presented. The results of the thermal characterization support the theoretical
considerations.
This work investigates a packaging solution for high voltage semiconductors (20 kV), allowing for a dramatic reduction in size and complexity of power electronics modules. The standard packaging structures typically introduce a competition between electrical insulation (which requires thick insulating layers) and thermal performance (where thin, high thermal conductivity layers are preferred). Here, we introduce a concept which addresses this competition and is based on direct cooling using dielectric liquid. Single-chip heatsinks are designed, optimized using computational fluid dynamics (CFD), built and tested.
This work investigates a packaging solution for high power density semiconductors (> 200 W/cm 2), allowing for a dramatic reduction in size and complexity of power electronics modules. The multiple layers in standard packaging structures degrade the cooling efficiency due as they lengthen the path between dies and heatsinks. Here, we reduce the layer count by merging the ceramic substrate and the heat exchanger in a single part. CFD simulations and experimental validation are performed on a single-chip cooling packaging, and demonstrate a 10-20 % reduction in thermal resistance over more traditional cooling solutions.
Embedding power semiconductor devices in pre-packages may enable low-inductive power semiconductor module designs with superior thermal performance and reliability. However, it is crucial to understand mechanical stress formation due to the differences in thermal expansion of the materials used. This paper presents a systematic study of thermomechanical stresses in Si and SiC power semiconductor pre-packages based on PCB embedding or compression molding. The analysis is based on thermomechanical FEM simulations and complemented by passive thermal cycling of different test carrier designs. Patterning and CTE-matching of contacts are proven as strategies to minimize thermomechanical stress.
This paper presents design, fabrication, and analysis of a PCB embedded half-bridge. Here, a pre-package that contains a 100 V / 100 A MOSFET half bridge is fabricated and embedded into a converter level power PCB, allowing for two routing layers on top of the semiconductors. This enables to minimize the commutation loop inductance by placing a decoupling capacitor directly on top of the switches. Experimentally a parasitic inductance of 1.4 nH is deducted from the ringing frequency in switching experiments. The second design goal is an optimized thermal
performance. Both, simulation with ANSYS Icepak and experiments indicate a value of 1.77 K/W. Based on the results, a 12 V / 48 V bidirectional converter was implemented and operated with a maximum power of 620 W.
PCB embedding in combination with direct-bonded copper (DBC) substrates is an attractive approach for packaging of power semiconductors facilitating low-inductive designs while relying on a proven insulating material. However, the CTE mismatch of these materials could cause reliability issues. This study presents an initial reliability screening using simple IGBT prepackages with alumina-based DBC as test vehicles. After -40/150 °C temperature cycles, fracture of the substrate and the chip is observed, resulting in an increased on-state resistance. Literature data suggest that the substrate failure is independent from the embedding. To gain a deeper understanding of the limitations of the technology, further research with optimized DBC substrates is required.
This paper presents a novel fabrication concept for PCB embedded power semiconductors. Here, the semiconductors are attached to an insulated metal substrate, which is embedded in a second step into an almost-ready PCB. This approach avoids handling of bare dies during PCB production. To demonstrate the feasibility of the concept, a 1200 V / 50 A B6 bridge is designed and fabricated. The performance is evaluated and benchmarked. Compared to a conventional DBCbased power module, the conduction losses are reduced by 21% and the thermal resistance is reduced by 29%. Turn-off losses are 25% lower, while turn-on losses are about the same for both module types. A further optimization of the switching performance is possible, but requires a reduced DC-link inductance and an optimization of the gate resistance.
This paper presents a modular fabrication concept for printed circuit board embedded power semiconductors. The fabrication is done in a two step approach. First, the Single-Switch-Pre-Packages (SSPP) are built using standard embedding processes. Subsequently, full converters are fabricated by embedding of the SSPP as functional inlays into a PCB-power module. For optimal heat spreading, the semiconductor dies are silver sintered on a thick copper substrate. To exploit further the potential of the substrate, heat exchanger structures are chemically etched on it. Dielectric coolant serves as the cooling medium in this case. Laboratory demonstrators are built and characterization is performed as proof-of-concept. Thermal test indicates an junction to ambient thermal resistance of 0.43 K/W, compared to 0.8 K/W for reference module on a standard cold plate with water glycol. The hydraulic power and coolant temperature were identical for both cases.