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Embedding power semiconductor devices in pre-packages may enable low-inductive power semiconductor module designs with superior thermal performance and reliability. However, it is crucial to understand mechanical stress formation due to the differences in thermal expansion of the materials used. This paper presents a systematic study of thermomechanical stresses in Si and SiC power semiconductor pre-packages based on PCB embedding or compression molding. The analysis is based on thermomechanical FEM simulations and complemented by passive thermal cycling of different test carrier designs. Patterning and CTE-matching of contacts are proven as strategies to minimize thermomechanical stress.
PCB embedding in combination with direct-bonded copper (DBC) substrates is an attractive approach for packaging of power semiconductors facilitating low-inductive designs while relying on a proven insulating material. However, the CTE mismatch of these materials could cause reliability issues. This study presents an initial reliability screening using simple IGBT prepackages with alumina-based DBC as test vehicles. After -40/150 °C temperature cycles, fracture of the substrate and the chip is observed, resulting in an increased on-state resistance. Literature data suggest that the substrate failure is independent from the embedding. To gain a deeper understanding of the limitations of the technology, further research with optimized DBC substrates is required.