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Wide bandgap semiconductors, SiC and GaN-based power devices represent key candidates in the development of more efficient devices due to their superior electrical and thermal properties compared to silicon. To achieve maximal performance from WBG semiconductors, new packaging technologies and thermo-electric designs must be developed to ensure efficient and fast switching of devices while minimizing losses. The paper aims to investigate the thermal and mechanical behavior of new prepackage embedding technologies by finite element simulation. The focus is on insulated substrates including direct bonded copper (DBC) with various dielectrics such as AlN, Al 2O 3, Si3N 4 and new insulated metal substrates (IMS) with emphasis on commercially available materials and thicknesses. This study proposes a thermo-mechanical pareto-optimization methodology able to identify the best substrate configuration. The sintered silver layer (in both sides of the chip), which is the most prone to failure due to delamination, has been modelled with a temperature-dependent bilinear hardening model to account for plasticity. Pareto-optimization accounts for the module thermal resistance and the plastic strain or Von Mises Stress in the sintered layer. Results demonstrate that the best candidate from the thermo-mechanical point of view is the DBC with AlN showing a thermal resistance of 0.34 K/W, accumulative plastic strain of 0.18 % and Von Mises stress of 274 MPa. Finally, the parasitic inductance of multiple pre-packages is evaluated to scale the power of the module. Proper design allows to achieve a stray inductance as small as 1.23 nH for two prepackages and 2.85 nH for four prepackages.
Horizontal chip cracks have been reported in various scientific publications on PCB embedded power semiconductor devices. This study investigates in detail the root cause of the cracks. Experimental evidence indicates that the chip fractures in the mechanical grinding process during preparation of the cross-sections. Here, two different factors are relevant: First, the mechanical fracture strength of the semiconductor die decreases when grinding its edge. The use of P320 sand paper reduces the characteristic fracture strength from 719 MPa to 211 MPa. Second, the tensile stresses in the chip edge increase considerably when, part of the die and package is removed by grinding. Both effects together result in a failure probability of 100%. The use of finer grain sandpaper for target preparation helps to reduce the probability of generating horizontal chip cracks during cross-sectioning.
This study investigated the thermal performance of a packaging solution designed to manage the electrical isolation and cooling of high voltage ( ) SiC power semiconductor > 3300 V devices. The proposed packaging merges the ceramic substrate and the heat exchanger into a single component, streamlining the overall design. Specifically, a novel heat exchanger is developed for a multi-chip module (20 kV), utilizing a combination of jet impingement and channel- flow cooling techniques. Computational fluid dynamics (CFD) simulations and experimental validation are conducted on a multi-chip module to assess the thermal resistance of this new cooling solution. The results demonstrate a
low thermal resistivity of 0.118 cm2K/W, indicating the potential for improved cooling performance in high voltage and power density semiconductor applications.
Tests are carried out on two different series-connected switches made of six SiC MOSFETs capable of blocking 10 kV and 20 kV respectively. High voltage capacitors are connected to the drain terminals of the MOSFETs to emulate the common mode currents’ paths due to parasitic capacitances of the packaging. Due to high dV/dt, common mode currents become dangerous to the switch as they unsettle the voltage sharing during turn-off and unbalance switching losses. This could lead some of the MOSFETs to experience avalanche breakdown. A novel packaging approach that suppresses or balances the common mode currents is introduced.
Gallium nitride transistors have a smaller die area compared to silicon-based devices, which can lead to thermal challenges in high current density applications. Therefore, thermally optimized packages with a high heat spreading capability in combination with small parasitic are necessary. This work investigates the thermal performance a 7 mΩ, 100 V GaN HEMT in a thermally optimized single chip package with integrated RTD and compares it to the commercial counterpart. The thermal optimized package shows a significantly better transient thermal impedance resulting in a static thermal resistance of 3.1 K/W, which is a 20 % reduction in comparison to the COTS package. The integrated RTD trace has a relative reaction time of 590 ms, which is 30-fold slower in comparison to the junction temperature. To show the identical electrical behavior, although the single chip package is larger, it is compared with the commercial off-the-shelf package and a 5 mΩ, 100 V GaN single chip package in a 300 kHz, 48 V buck converter. Both 7 mΩ versions have identical efficiencies of ≈97.5 % up to 50 A output current, slightly outperforming the 5 mΩ GaN transistor. With its combination of improved thermal characteristics and lowinductance, the thermally optimized package of the GaN device offers more degrees of freedom in the design of power converter to exploit trade-offs between longer lifetime, higher temperature operation and power density. Index Terms—gallium nitride, high electron mobility transistor, (thermal) performance evaluation, thermally optimized package, DC/DC converter, high current application, parallelization
In this work an approach for a direct experimental comparison of the application-oriented performance between two high current GaN DC/DC converters based on 7mΩ, 100V GaN HEMTs in a commercial off-the-shelf top-cooled package and 5mΩ, 100V GaN HEMTs embedded in a thermally-optimized single-chip package is given. The two packaging versions are compared by a maximally identical implementation of the power and gate loops in a 48V, 300kHz buck converter with two parallel GaN HEMTs. In the single-chip package the die is directly mounted on a 12×6mm 2 copper-heat spreader offering a significantly lower thermal resistance to heatsink (1.69KW −1 ) in comparison to the commercial off-the-shelf version (2.45KW −1 ). For a direct benchmark, the COTS-based converter has an identical power-loop to the SCP-version with a novel gate-drive concept. Both versions have an efficiency of 96.8% at 65A output current (output power: 1.5kW), while the commercial off-the-shelf version has a better efficiency for lower currents, due to its better hard-switching Figure-of-Merits and therefore lower switching losses and reaches an output current of up to 80A (output power: 1.75kW). A detailed analytical loss breakdown for the different transistors in dependence of the temperature and output current is given to proof the measured current point, where the efficiencies of both converters are identical, since the higher switching losses of the SCP version are compensated by lower conduction losses at higher currents and temperatures compared to the smaller COTS transistor. Finally, an outlook on further improvements for reaching higher output currents and potential converters for a more fair comparison of different thermally optimized SMD packages are given.
Das Einbetten von Halbleiterbauelementen stellt einen innovativen Ansatz für die Aufbau- und Verbindungstechnik (AVT) leistungselektronischer Systeme dar. Im Rahmen von zahlreichen Forschungsvorhaben wurde gezeigt, dass im Vergleich zu einer konventionellen AVT geringere parasitäre Induktivitäten und Widerstände [1, 2]und damit geringere Leitungs- und Schaltverluste ermöglicht werden. Auch kann der thermische Widerstand durch den Einsatz von Dickkupfersubstraten und wärmeleitfähigen organischen Isolatoren erheblich reduziert werden [2, 3, 4]. Dadurch lässt sich auf Systemebene eine höher Leistungsdichte erreichen [5], ohne dass dadurch die Lastwechselfestigkeit leidet [6, 3].
Dennoch findet die Technologie bis heute nur im Low-Power Bereich oder zum Chip-Scale Packaging von einzelnen Leistungsschaltern kommerziellen Einsatz.
Dieser Vortrag diskutiert mögliche Hemmnisse und Grenzen der Technologie.
This work investigates a packaging solution for high power density semiconductors (> 200 W/cm 2), allowing for a dramatic reduction in size and complexity of power electronics modules. The multiple layers in standard packaging structures degrade the cooling efficiency due as they lengthen the path between dies and heatsinks. Here, we reduce the layer count by merging the ceramic substrate and the heat exchanger in a single part. CFD simulations and experimental validation are performed on a single-chip cooling packaging, and demonstrate a 10-20 % reduction in thermal resistance over more traditional cooling solutions.
The ever-increasing switching speed of semiconductor devices requires a precise measurement of steep current transients. The M-shunt concept offers high signal fidelity, good cooling, and simple manufacturing. Depending on the resistive material used, temperature as well as skin and proximity effects impede static and dynamic measurements to a different degree. A step forward has been derived from the ideal coaxial shunt, so far, a purely theoretical concept, which is hardly producible due to its sophisticated structure. By transferring this concept to the M-shunt structure with its improved PCB manufacturing technologies it can now be realised in practice. Nevertheless, the calibration and the correct degree of delay compensation remain challenging and are investigated more closely within this paper. Furthermore, it will be discussed why the conventional method of bandwidth determination doesn't work for the M-shunt structure. In addition to the low inductance introduced into the load circuit, the high bandwidth of the shunts could be demonstrated, as well as the possibility to extend this by design rules. Supplemented by the advantages of the lower load inductance, the M-shunt will become the tool of choice for characterising switching transients at least up to 200 MHz required bandwidth eventually. Although it is obviously difficult to improve the 3 dB bandwidth with suitable design rules, the range of nearly entirely unaffected measurement frequencies (e.g. < 1 dB) can be significantly extended by limited coupling. For even higher frequencies, measurements of the current M-shunt models, as well as for the coaxial shunts used as reference, should be corrected by post processing to get precise measurement results.
Previously, a novel concept for PCB embedding of power semiconductors with reinforced top contacts has been published by our group. In this work, a thermomechanical study is performed to understand the fracture probability of the chip during fabrication. The ball-on-ring (BOR) and ball-on-edge (BOE) tests are employed to characterize the chip strength. A probabilistic model is used to evaluate the failure probability. The contribution of different fabrication steps to the overall failure probability is investigated. A parametric analysis is performed to analyze the impact of material choice and the thickness of the substrate and the interposer. A single-step sintered package with a 200 μm thick Cu interposer and an 800 μm thick Cu substrate with hard Cu leads to a 12% failure probability compared to 52% for an identical stack with a soft Cu substrate. The top surface failure probability for a 150 μm thick CIC interposer is 0.016% compared to 8.6% for a 100 μm Cu interposer., for an identical 800μm thick Cu substrate. A sinterlamination process, where the die-attach and curing of the prepreg material simultaneously take place, results in a 0.03% failure probability.
This work investigates a packaging solution for high voltage semiconductors (20 kV), allowing for a dramatic reduction in size and complexity of power electronics modules. The standard packaging structures typically introduce a competition between electrical insulation (which requires thick insulating layers) and thermal performance (where thin, high thermal conductivity layers are preferred). Here, we introduce a concept which addresses this competition and is based on direct cooling using dielectric liquid. Single-chip heatsinks are designed, optimized using computational fluid dynamics (CFD), built and tested.
PCB embedding is an attractive packaging technology for highly integrated future power systems. Electrical and thermal benefits and limitations are well understood, but only few publications focus on reliability. Here we are addressing high-humidity high temperature reverse bias (H3TRB) tests, which are performed to gain deeper understanding of the limitations of this technology. Cu filament growth is observed on both, PCB embedded samples and silicone potted reference samples. These filaments may form a conductive path and lead to an increased leakage current in blocking mode. Electrochemical corrosion of the Cu-plated guard ring is identified as root cause.
Embedding power semiconductor devices into printed circuit boards (PCB) provides several benefits compared to conventional packaging technologies. Integrating the semiconductor dies into the circuit board reduces the converter size. This results in short current loops, enabling low interconnection resistances and parasitic inductances. Both contribute to a higher system-level efficiency, as conduction and switching losses are reduced. Moreover, the use of thick Cu substrates allows efficient heat removal, due to a low thermal resistance. Therefore, PCB embedding has received a lot of attention in the power electronics community for more than a decade. This article aims to provide a comprehensive review of the scientific literature on the topic ranging from basic fabrication technology over module or system-level demonstrators for electrical and thermal testing to reliability studies. Performance indicators, such as the commutation loop inductance Lσ, the chip area independent thermal resistance Rth × Achip, allow a comparison of different approaches and benchmarking with conventional power modules. Several publications report stray inductances below 1 nH and chip area independent thermal resistances in the range of 20…30 mm²K/W.
Most current measurement techniques suffer from temperature impacts, though to a different degree. This is also true for shunt resistors, which are usually improved significantly by using temperature compensated alloy materials like Manganin(r) or by proper calibration and subsequent temperature compensation. The concept of the copper-based PCB M-shunt has already been reported to yield excellent current measurement results at room temperature. However, due to the high-temperature coefficient of copper (3920 ppm/K), the current measurement with those M-shunts showed considerable measurement errors for high temperatures and due to self-heating. This can be improved by the use of Manganin. However, still the connection of the resistor with the copper of the PCB and their respective thermal behavior needs to be considered as further possible sources of error. This paper presents challenges associated with the improvement of PCB-based shunts by temperature-compensated material, while not compromising the critical issue of bandwidth and manufacturing capability. It explicitly addresses the problems and difficulties as reported for previous development stages. In its new version, the M-shunt, represents a low inductance measurement system that can be optimised for much higher energies than the coax shunt, while not increasing the inductance introduced into the circuit. Alternatively, it can be configured for a significantly increased bandwidth and lower inductance compared to its coaxial reference.
Embedding power semiconductor devices in pre-packages may enable low-inductive power semiconductor module designs with superior thermal performance and reliability. However, it is crucial to understand mechanical stress formation due to the differences in thermal expansion of the materials used. This paper presents a systematic study of thermomechanical stresses in Si and SiC power semiconductor pre-packages based on PCB embedding or compression molding. The analysis is based on thermomechanical FEM simulations and complemented by passive thermal cycling of different test carrier designs. Patterning and CTE-matching of contacts are proven as strategies to minimize thermomechanical stress.
Thermal impedance evaluation of optimized PCB-based GaN HEMT Single-ChipPrepackage using VGS Method
(2022)
This study evaluates the measurement of the thermal resistance and impedance of GaN HEMTs packages with gatesource voltage (VGS) for junction temperature measurement. First, calibration measurement of VGS vs temperature is performed in an oven. Large deviations from chip to chip require that each device is calibrated separately. Zth is measured for an experimental single-chip prepackage (SCP), developed in our lab, and a commercial reference package (GaNpx). The measured junction to ambient thermal resistance of the SCP is 35% lower compared to the reference. This is caused by a copper heat spreader integrated in the package. The thermal resistance of multiple packages attached on one PCB is also performed. This measurement indicates a maximum difference of 35%. This difference remained the same in several experiments with two thermal interface materials and pressure levels.
This paper presents design, fabrication, and analysis of a PCB embedded half-bridge. Here, a pre-package that contains a 100 V / 100 A MOSFET half bridge is fabricated and embedded into a converter level power PCB, allowing for two routing layers on top of the semiconductors. This enables to minimize the commutation loop inductance by placing a decoupling capacitor directly on top of the switches. Experimentally a parasitic inductance of 1.4 nH is deducted from the ringing frequency in switching experiments. The second design goal is an optimized thermal
performance. Both, simulation with ANSYS Icepak and experiments indicate a value of 1.77 K/W. Based on the results, a 12 V / 48 V bidirectional converter was implemented and operated with a maximum power of 620 W.
Thermisch und elektrisch optimiertes Leiterplatten-Prepackage für 100V/100A GaN Leistungshalbleiter
(2021)
In dieser Arbeit wird ein Integrationskonzept für GaN Leistungshalbleiter in Leiterplattentechnologie vorgestellt. Das
Konzept beruht auf thermisch optimierten Prepackages mit integrierten Temperatursensoren, die in Leiterplattenembeddingtechnologie hergestellt werden. Durch ein asymmetrisches Layout wird ein niederinduktiver Kommutierungskreis ermöglicht. Funktionsmuster mit einem 100 V / 120 A GaN HEMT wurden aufgebaut und erprobt. Die Bauteile sind elektrisch voll funktionsfähig und weisen einen thermischen Widerstand von 3,34 K/W auf. Dieser Wert liegt 35% unter dem eines kommerziellen Referenzbauteils.
The embedding of power electronics components into the PCB increases their thermal and electrical performance. Due to lower parasitic inductances and a lower thermal resistance, the overall power density of the system can be increased. However, there is a lack on studies about the reliability of PCB embedded power electronics, especially under humidity stress. This study uses test vehicles with functional diodes embedded into the PCB. The reliability of the test vehicles is studied under HV-H3TRB conditions. A critical leakage current is observed after 200h with a benzoxazine based prepreg and after 600h for an epoxy based prepreg. A rootcause analysis revealed lift-off of the polyimide layer and subsequent electrochemical corrosion as failure mechanism. The delamination is most likely triggered by the Au surface on the chips top metal pad. A second set of test samples was fabricated using an improved surface treatment before lamination. 75% of these samples passed the 1000h H3TRB test successfully.