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In this work an approach for a direct experimental comparison of the application-oriented performance between two high current GaN DC/DC converters based on 7mΩ, 100V GaN HEMTs in a commercial off-the-shelf top-cooled package and 5mΩ, 100V GaN HEMTs embedded in a thermally-optimized single-chip package is given. The two packaging versions are compared by a maximally identical implementation of the power and gate loops in a 48V, 300kHz buck converter with two parallel GaN HEMTs. In the single-chip package the die is directly mounted on a 12×6mm 2 copper-heat spreader offering a significantly lower thermal resistance to heatsink (1.69KW −1 ) in comparison to the commercial off-the-shelf version (2.45KW −1 ). For a direct benchmark, the COTS-based converter has an identical power-loop to the SCP-version with a novel gate-drive concept. Both versions have an efficiency of 96.8% at 65A output current (output power: 1.5kW), while the commercial off-the-shelf version has a better efficiency for lower currents, due to its better hard-switching Figure-of-Merits and therefore lower switching losses and reaches an output current of up to 80A (output power: 1.75kW). A detailed analytical loss breakdown for the different transistors in dependence of the temperature and output current is given to proof the measured current point, where the efficiencies of both converters are identical, since the higher switching losses of the SCP version are compensated by lower conduction losses at higher currents and temperatures compared to the smaller COTS transistor. Finally, an outlook on further improvements for reaching higher output currents and potential converters for a more fair comparison of different thermally optimized SMD packages are given.
To make the full performance of the intrinsic 100 V, 5 mΩ gallium nitride transistors available on system level, in this work an asymmetrical & thermally optimized PCB embedded single chip package with integrated resistance thermometer, high temperature capability and a thermal resistance Rth,j−hs of 3.3 K W−1 is characterized in a 48 V to 24 V 300 kHz mild-hybrid DC/DC operation with two paralleled chips in each low- (LS) and high-side (HS). The transistors are mounted on a 4-layer multilayer PCB with 1 mm copper inlays to achieve a high current capability, while allowing narrow logic traces on the same PCB. The designed converter is achieving a light load efficiency of ≥99 % and an efficiency of 97 % at 60 A output current and ≈1.3 kW output power in a 48 V to 24 V 300 kHz buck-converter operation. The on-board temperature readout circuit and the phase output current sensor offer the possibility to extend the GaN transistors to an intelligent power module by the compact and simple sensors.
Thermisch und elektrisch optimiertes Leiterplatten-Prepackage für 100V/100A GaN Leistungshalbleiter
(2021)
In dieser Arbeit wird ein Integrationskonzept für GaN Leistungshalbleiter in Leiterplattentechnologie vorgestellt. Das
Konzept beruht auf thermisch optimierten Prepackages mit integrierten Temperatursensoren, die in Leiterplattenembeddingtechnologie hergestellt werden. Durch ein asymmetrisches Layout wird ein niederinduktiver Kommutierungskreis ermöglicht. Funktionsmuster mit einem 100 V / 120 A GaN HEMT wurden aufgebaut und erprobt. Die Bauteile sind elektrisch voll funktionsfähig und weisen einen thermischen Widerstand von 3,34 K/W auf. Dieser Wert liegt 35% unter dem eines kommerziellen Referenzbauteils.
The use of packaging technologies which allow thick leadframes and thus a high heat spread with metal substrates close to semiconductors, promise a better thermal performance of power modules, especially when using modern GaN or SiC power transistors with high power density. However, the degrees of freedom in the dimensioning of these metal substrates with regard to area, thickness, symmetry and chip positioning are large and optimization towards minimum thermal resistance results in unnecessarily large and unmanufacturable leadframes with high parasitic inductance, which hinders fast switching. In this paper the influence of geometric parameters of the leadframe on the thermal performance is investigated based on thermostatic 3D FEM simulations of a half-bridge with symmetrical losses. From this thermal analysis the dimensioning for a GaN half-bridge with high thermal requirements for a low inductance commutation cell is derived.
This paper proposes an asymmetric Single-Chip-Prepackage (SCP) with thick Cu substrate for the optimum electrical and thermal performance of the GaN-HEMT devices. Additionally, the package features a Ni-based integrated thermistor. Laboratory demonstrators have been fabricated using PCB embedding technology. A full electrical characterization of the packaged device indicates full functionality. The temperature coefficient of the integrated temperature sensor is 𝛼 = 0.00541 /𝐾. Thermal characterization of the SCP shows a junction to heatsink thermal resistance Rth,jh = 3.34 K/W, which is 36 % less than the commercial reference device. A silver sinter based assembly process for system integration of SCP is introduced in view of a planar thermal interface. In a 300 kHz 48 V to 24 V buck-converter operation with 60 Arms output current, a 98% efficiency is achieved.
Gallium nitride transistors have a smaller die area compared to silicon-based devices, which can lead to thermal challenges in high current density applications. Therefore, thermally optimized packages with a high heat spreading capability in combination with small parasitic are necessary. This work investigates the thermal performance a 7 mΩ, 100 V GaN HEMT in a thermally optimized single chip package with integrated RTD and compares it to the commercial counterpart. The thermal optimized package shows a significantly better transient thermal impedance resulting in a static thermal resistance of 3.1 K/W, which is a 20 % reduction in comparison to the COTS package. The integrated RTD trace has a relative reaction time of 590 ms, which is 30-fold slower in comparison to the junction temperature. To show the identical electrical behavior, although the single chip package is larger, it is compared with the commercial off-the-shelf package and a 5 mΩ, 100 V GaN single chip package in a 300 kHz, 48 V buck converter. Both 7 mΩ versions have identical efficiencies of ≈97.5 % up to 50 A output current, slightly outperforming the 5 mΩ GaN transistor. With its combination of improved thermal characteristics and lowinductance, the thermally optimized package of the GaN device offers more degrees of freedom in the design of power converter to exploit trade-offs between longer lifetime, higher temperature operation and power density. Index Terms—gallium nitride, high electron mobility transistor, (thermal) performance evaluation, thermally optimized package, DC/DC converter, high current application, parallelization