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Patterning and CTE-matching of contacts to optimize thermomechanical stress in power semiconductor pre-packages

  • Embedding power semiconductor devices in pre-packages may enable low-inductive power semiconductor module designs with superior thermal performance and reliability. However, it is crucial to understand mechanical stress formation due to the differences in thermal expansion of the materials used. This paper presents a systematic study of thermomechanical stresses in Si and SiC power semiconductor pre-packages based on PCB embedding or compression molding. The analysis is based on thermomechanical FEM simulations and complemented by passive thermal cycling of different test carrier designs. Patterning and CTE-matching of contacts are proven as strategies to minimize thermomechanical stress.

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Author:Niko Pavlicek, Chunlei Liu, Patrick Stalder, Giovanni Salvatore, Fabian Mohn, Till HuesgenORCiD, Tina Thomas
URL / DOI:https://ieeexplore.ieee.org/abstract/document/9861980
Identifier:978-3-8007-5757-2 OPAC HS OPAC extern
Parent Title (English):CIPS 2022; 12th International Conference on Integrated Power Electronics Systems
Publisher:VDE
Place of publication:Berlin
Document Type:conference proceeding (article)
Conference:CIPS 2022; 12th International Conference on Integrated Power Electronics Systems, March, 15-17, 2022, Berlin, Germany
Language:English
Year of first Publication:2022
Tag:ARCHIVE
Number of pages:7 Seiten
First Page:224
Last Page:230
Institutes:Fakultät Elektrotechnik
Research focus:FSP1: Energie
FSP3: Produktion
Publication Lists:Huesgen, Till
Research Project:ARCHIVE – ARchitecture Ceramic for HIgh Voltage power Electronics
Publication reviewed:begutachtet
Release Date:2022/11/10
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