TY - CHAP A1 - Manke, Philip A1 - Schäferling, Michael A1 - Kiefer, Gundolf T1 - Using the ASTERICS Framework for Rapid Prototyping and Education in Image Processing on FPGAs T2 - Embedded World Conference 2020 KW - computer vision KW - embedded vision KW - toolchains KW - image processing KW - FPGA KW - Python KW - VHDL Y1 - 2020 UR - https://ees.tha.de/asterics/asterics-paper-ew2020.pdf ER - TY - CHAP A1 - Bahle, Alexander A1 - Kiefer, Gundolf A1 - Pfützner, Anne Kerstin A1 - Vollbracht, Lutz T1 - The ParaNut/RISC-V Processor - An Open, Parallel, and Highly Scalable Processor Architecture for FPGA-based Systems T2 - Embedded World Conference 2020 KW - RISC-V KW - processor architecture KW - FPGA KW - SIMD Y1 - 2020 UR - https://ees.tha.de/paranut/paranut-paper-ew2020.pdf ER - TY - CHAP A1 - Schubaur, Philipp A1 - Knauer, Peter A1 - Merli, Dominik T1 - FISMOS - An FPGA Implementation of a Security Module as Open Source T2 - The 18th International Conference on Availability, Reliability and Security (ARES 2023) KW - embedded security KW - FPGA KW - RISC-V KW - security modul KW - SoC Y1 - 2023 SN - 979-8-4007-0772-8 U6 - https://doi.org/10.1145/3600160.3605168 ER -